CYRF69103-40LFXC Cypress Semiconductor Corp, CYRF69103-40LFXC Datasheet
CYRF69103-40LFXC
Specifications of CYRF69103-40LFXC
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CYRF69103-40LFXC Summary of contents
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... Pb-free 40-Pin QFN Package ■ Advanced Development Tools based on Cypress’s PSoC ■ Tools 470nF Radio Function P1.5/MOSI P1.4/SCK P1.3/nSS 12 MHz • 198 Champion Court • San Jose CYRF69103 ® 47µ µF RFbias RFp RFn IRQ/GPIO MISO/GPIO XOUT/GPIO PACTL/GPIO . . . . . . . . . . . . 470 95134-1709 • ...
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... Microcontroller Function Register Summary ............. 55 Radio Function Register Summary............................... 57 Absolute Maximum Ratings .......................................... 58 DC Characteristics (T = 25×C) ....................................... 58 AC Characteristics ........................................................ 60 RF Characteristics.......................................................... 64 Ordering Information...................................................... 66 Package Handling........................................................... 66 Package Diagram............................................................ 66 Document History Page ................................................. 67 Sales, Solutions, and Legal Information ...................... 68 Worldwide Sales and Design Support....................... 68 CYRF69103 Page [+] Feedback ...
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... The PRoC LP includes a Watchdog timer, a vectored interrupt controller, a 12-bit programmable interval timer with configurable 1 ms interrupt and a 16-bit free running timer. In addition, the CYRF69103 IC has a Power Management Unit (PMU), which enables direct connection of the device to any battery voltage in the range 1.8V to 3.6V. The PMU conditions the battery voltage to provide the supply voltages required by the device and may supply external devices ...
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... Backward Compatibility The CYRF69103 IC is fully interoperable with the main modes of the first generation Cypress radios namely the CYWUSB6934 -LS and CYWWUSB6935-LR devices. The 62.5 kbps mode is supported by selecting 32 chip DDR mode. Similarly, the 15.675 kbps mode is supported by selecting 64 chip SDR mode ...
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... Sets the number of consecutive symbols for non-correlation to detect end of packet. AAAA are the two preamble bytes. Any other byte can also be written into the preamble register file. Recommended counts of the preamble bytes to be sent must be >8. CYRF69103 Page [+] Feedback ...
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... Buffered CLK, PACTL_n or Radio GPIO Document #: 001-07611 Rev *F Figure 7-1. Pin Diagram Corner tabs P0 XTAL 2 29 CYRF69103 WirelessUSB BAT1 P2 BAT2 * E-PAD Bottom Side BIAS Description CYRF69103 XOUT / GPIO MISO / GPIO P1.5 / MOSI IRQ / GPIO P1.4 / SCK P1 P1.2 V DD_Micro P1.1 P1.0 Page [+] Feedback ...
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... SOP. In particular the length, data, and CRC16 are all –15 sent in the same mode. In general, lower data rates reduces –20 packet error rate in any given environment. –25 The CYRF69103 IC supports the following data rates: –30 1000 kbps (GFSK) ■ 250 kbps (32-chip 8DR) ■ ...
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... The CYRF69103 IC supports packet length bytes; interrupts are provided to allow an MCU to use the transmit and receive buffers as FIFOs. When transmitting a packet longer than 16 bytes, the MCU can load 16 bytes initially, and add further bytes to the transmit buffer as transmission of data creates space in the buffer ...
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... SS12 diode must be used to stay within this linear range of operation. Along with the diode, the inductor used must not saturate its core. In higher loads, a lower resistance/higher saturation coil like the inductor from Sumida must be used. CYRF69103 drops below a CC Page [+] Feedback ...
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... Figure 8-4. PMU Disabled - External Boost Converter 0.047 µF 1 Ohm 1% 47 Ohm 0.047µF 10 µF 6. DD_MICRO 0.1µF CYRF69103 V CC 0.047µF 0.047µF 0.047µF 0.047µF 0.047µF 0.047µF PRoC LP V External DC-DC CC Boost Converter 10µ ...
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... MOSI function on MCU function high-impedance state whenever SS is high. Figure 9-2. 4-Wire SPI Mode MCU Function P1.5/MOSI MOSI P1.6/MISO P1.4/SCK SCK P1.3/nSS nSS This connection is external to the PRoC LP Chip CYRF69103 Radio Function Radio Function MISO Page [+] Feedback ...
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... SPI I/O Voltage References The SPI interfaces between MCU function and the radio and the IRQ and RST have a separate voltage reference V CYRF69103 V is normally set 9.5 SPI Connects to External Devices The three SPI wires, MOSI, SCK, and SS are also drawn out of ...
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... Bits 7:0 CPU Accumulator [7:0] 8-bit data value holds the result of any logical/arithmetic instruction that uses a source addressing mode. Document #: 001-07611 Rev * XIO Super Carry – R CPU Accumulator [7:0] – – – CYRF69103 Zero Global – – – Page [+] Feedback ...
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... Document #: 001-07611 Rev * [7:0] – – – Stack Pointer [7:0] – – – Program Counter [15:8] – – – Program Counter [7:0] – – – CYRF69103 – – – – – – – – – – – – Page [+] Feedback ...
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... In this case, the value in the memory location at address 7 is added with the Accumulator, and the result is placed in the memory location at address 7. The Accumulator is unchanged. MOV REG[8 this case, the Accumulator is moved to the register space location at address 8. The Accumulator is unchanged. CYRF69103 Page [+] Feedback ...
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... Operand 2 Immediate Value Table 12-8. Destination Direct Source Direct Opcode Instruction Example MOV [7], CYRF69103 Operand 1 Operand 2 Destination Index Immediate Value 5 In this case, the value in the memory location at address X+7 is added with the immediate value of 5 and the result is placed in the memory location at address X+7 ...
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... Table 12-10. Destination Indirect Post Increment Opcode Operand 1 Instruction Destination Address Address Example MVI [8 this case, the value in the memory location at address indirect address. The Accumulator is moved into the memory location pointed to by the indirect address. The indirect address is then incremented. CYRF69103 Page [+] Feedback ...
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... MOV A, expr MOV A, [expr MOV A, [X+expr MOV [expr MOV [X+expr MOV [expr], expr MOV [X+expr], expr MOV X, expr MOV X, [expr MOV X, [X+expr] CYRF69103 Instruction Format Flags MOV [expr MOV MOV MOV A, reg[expr MOV A, reg[X+expr MOV [expr], [expr MOV reg[expr MOV reg[X+expr ...
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... Free Running Timer Wrap 0x0048 INT2 0x004C Reserved 0x0050 GPIO Port 2 0x0054 Reserved 0x0058 Reserved 0x005C Reserved 0x0060 Reserved 0x0064 Sleep Timer 0x0068 Program Memory begins here (if below interrupts not used, program memory can start lower) 0x1FFF CYRF69103 Page [+] Feedback ...
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... CYRF69103 enables this type of in-system programming by using the P1.0 and P1.1 pins as the serial programming mode interface. This allows an external controller to cause the CYRF69103 to enter serial programming mode and then to use the test queue to issue Flash access functions in the SROM. Document #: 001-07611 Rev *F Figure 14-2 ...
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... The SWBootReset function does not execute when the SSC instruction is executed with a bad key value and a nonzero function code. A CYRF69103 device executes the HALT instruction if a bad value is given for either KEY1 or KEY2. The SWBootReset function verifies the integrity of the calibration data by way of a 16-bit checksum, before releasing the M8C to run user code ...
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... For a CPU speed of 12 MHz set to 56h Document #: 001-07611 Rev *F 14.5.5 ProtectBlock Function The CYRF69103 device offers Flash protection on a block-by-block basis. Table 14-7 lists the protection modes available. In the table, ER and EW are used to indicate the ability to perform external reads and writes. For internal writes used ...
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... BLOCKID 0,FAh Table number to read Document #: 001-07611 Rev *F The table space for the CYRF69103 is simply a 64 byte row broken up into eight tables of eight bytes. The tables are numbered zero through seven. All user and hidden blocks in the CYRF69103 consist of 64 bytes. ...
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... The 32 kHz low power oscillator can be calibrated against the internal 24 MHz oscillator or another timing source if desired. CYRF69103 provides the ability to load new trim values for the 24 MHz oscillator based on voltage. This allows Vdd to be monitored and have firmware trim the oscillator based on voltage present ...
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... SROM Table Read Description The Silicon IDs for CYRF69103 devices are stored in SROM tables in the part, as shown in The Silicon ID can be read out from the part using SROM Table reads. This is demonstrated in the following pseudo code. As mentioned in the section “ ...
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... X ret 15.2 Clock Architecture Description The CYRF69103 clock selection circuitry allows the selection of independent clocks for the CPU, Interval Timers, and Capture Timers. CPU Clock The CPU clock, CPUCLK, can be sourced from the Internal 24 MHz oscillator ...
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... Hz Note Sleep intervals are approximate Bits 2:0 CPU Speed [2:0] The CYRF69103 may operate over a range of CPU clock speeds. The reset value for the CPU Speed bits is zero. Therefore, the default CPU speed is 3 MHz CPU Speed CPU when Internal ...
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... The programmable interval timer generates interrupt to the CPU on each reload. The parameters to be set appears on the device editor view of PSoC Designer after you place the CYRF69103 timer user module. The parameters ...
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... This value sets the size of each offset step for the internal oscillator. Nominal gain change (kHz/offsetStep) at each bit, typical conditions (24 MHz operation): Gain bit 0 = –1.5 kHz Gain bit 1 = –3.0 kHz Gain bit 2 = –6 kHz Gain bit 4 = –24 kHz Document #: 001-07611 Rev * Gain[4:0] R/W R/W R CYRF69103 rru tro lle R/W R/W R Page [+] Feedback ...
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... When the CPU enters sleep mode, the oscillator is stopped. When the CPU comes out of sleep mode it is running on the internal oscillator. The internal oscillator recovery time is three clock cycles of the Internal 32 kHz Low power Oscillator. Document #: 001-07611 Rev * kHz Bias Trim [1:0] R/W R/W R page 26. CYRF69103 kHz Freq Trim [3:0] R/W R/W R Page [+] Feedback ...
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... Default 0 0 The bits of the CPU_SCR register are used to convey status and control of events for various functions of a CYRF69103 device. Bit 7 GIES The Global Interrupt Enable Status bit is a read-only status bit and its use is discouraged. The GIES bit is a legacy bit, which was used to provide the ability to read the GIE bit of the CPU_F register ...
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... Bus Request Acknowledge (BRA) on the following positive edge of the CPU clock. The sleep logic waits for the following negative edge of the CPU clock and then asserts a system-wide Power Down (PD) signal. In page 33 the CPU is halted and the system-wide power down signal is asserted. CYRF69103 (Table 15-3). When ...
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... On the following CPUCLK, BRA is negated by the CPU and instruction execution resumes. Note that in on page 34 fixed function blocks, such as Flash, internal oscil- lator, EFTB, and bandgap, have about 15 µs start up. The wakeup times (interrupt to CPU operational) ranges from 75 µs to 105 µs. CYRF69103 Figure 17-2. Page [+] Feedback ...
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... S leep Tim interrupt occurs C LK32K IN T SLEEP PD BAN ABLE SAM PLE SAM PLE LVD / LK Scale) 24M Document #: 001-07611 Rev *F Figure 17-2. Wakeup Timing Interrupt is double sam pled by 32K clock and negated to system CYRF69103 restarted after (nom inal) Page [+] Feedback ...
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... This field controls the level below which the low voltage-detect trips—possibly generating an interrupt and the level at which the Flash is enabled for operation. VM[2:0] LVD Trip Point Typ. (V) 000 2.7 001 2.92 010 3.02 011 3.13 100 101 110 111 Document #: 001-07611 Rev * PORLEV[1:0] Reserved R/W R/W – CYRF69103 VM[2:0] R/W R/W R (Table Page [+] Feedback ...
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... Note This register can only be accessed in the second bank of I/O space. This requires setting the XIO bit in the CPU flags register Document #: 001-07611 Rev * Reserved – – – Table 18-1 on page 35 Reserved – – – CYRF69103 LVD PPOR – – – – Page [+] Feedback ...
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... Port 2 pins. Bits 7:2 P2 Data [7:2] Bits 1:0 P2 Data [1:0] Document #: 001-07611 Rev * P0.4/INT2 P0.3/INT1 - R/W R P1.5/SMOSI P1.4/SCLK P1.3/SSEL R/W R/W R Reserved - - CYRF69103 Reserved P0.1 Reserved - - R P1.2 P1.1 P1.0 R/W R/W R (Table 19- P2.1–P2.0 R/W R/W 0 ...
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... This register is used to configure P0.1. In the CYRF69103, only 8 mA sink drive capability is available on this pin regardless of the setting of the High Sink bit. If this pin is used as a general purpose output it draws current. This pin must be configured as an input to reduce current draw. ...
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... Int Act Low TTL Thresh Reserved R/W R/W – page 54 and Table 21-6 on page 53 Int Act Low TTL Thresh Reserved R/W R/W – CYRF69103 Open Drain Pull up Output Enable Enable R/W R/W R Open Drain Pull up Output Enable Enable R/W R/W R/W ...
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... Bit 2 see Section 19.2.5 Bit 1 Reserved Bit 0 see Section 19.2.7 Document #: 001-07611 Rev * Int Act Low Reserved Reserved R Int Act Low Reserved R/W – – CYRF69103 Reserved 5K pullup Output Enable enable - R/W R Open Drain Reserved Output Enable R/W – R section. OL3 ...
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... Section 19.2.7 Document #: 001-07611 Rev * Int Act Low TTL Reserved Threshold R/W R/W – Int Act Low Reserved High Sink R/W – R CYRF69103 Open Drain Pull up Output Enable Enable R/W R/W R Open Drain Pull up Output Enable Enable R/W R/W R/W 0 ...
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... Section 19.2.7 Document #: 001-07611 Rev * Int Act Low Reserved High Sink R/W – R Table 19-15 on page 45 Int Act Low Reserved High Sink R/W – R CYRF69103 Open Drain Pull up Output Enable Enable R/W R/W R Open Drain Pull up Output Enable Enable R/W R/W R ...
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... Section 19.2.7 19.3 GPIO Configurations for Low Power Mode To ensure low power mode, unbonded GPIO pins in CYRF69103 must be placed in a non-floating state. The following assembly code snippet shows how this is achieved. This snippet can be added as a part of the initialization routine. ...
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... SCK Clock Generation SCK Clock Select SCK Clock Phase/Polarity Select SCK GPIO Block Output Shift Buffer MISO/MOSI Master/Slave Set Crossbar SCK Shift Buffer LE_SEL Input Shift Buffer SCK_OE SS_N_OE MISO_OE MOSI_OE CYRF69103 SCK_OE SCK SS_N SS_N SS_N_OE MISO_OE MISO MOSI_OE MOSI Page [+] Feedback ...
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... For SPI Master mode, pin P1.4 must be configured as an output; for SPI Slave mode, pin P1.4 must be configured as an input. Document #: 001-07611 Rev * SPIData[7:0] R/W R/W R Comm Mode CPOL R/W R/W R page 42), the input/output direction of pins P1.3, P1.5, and P1.6 is set CYRF69103 R/W R/W R CPHA SCLK Select R/W R/W R Table 19-16 on page 46 shows the Page [+] Feedback ...
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... SSEL DAT SCLK SSEL DAT SSEL DAT A Document #: 001-07611 Rev *F Diagram LSB Bit 2 Bit 3 Bit 4 Bit 5 X LSB Bit 2 Bit 3 Bit 4 Bit 5 X LSB Bit 2 Bit 3 Bit 4 Bit 5 CYRF69103 Bit 6 Bit 7 MSB X X Bit 6 Bit 7 MSB X Bit 6 Bit 7 MSB Page [+] Feedback ...
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... Document #: 001-07611 Rev *F 20. Timer Registers All timer functions of the CYRF69103 are provided by a single timer block. The timer block is asynchronous from the CPU clock. The 16-bit free running counter is used as the time-base for timer captures and can also be used as a general time-base by software ...
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... This register holds the lower 8 bits of the timer. While writing into the 12-bit reload register, write lower byte first then the higher nibble. Document #: 001-07611 Rev * Free Running Timer [15:8] R/W R/W R Prog Interval Timer [7: Prog Interval Timer [11: Prog Interval [7:0] R/W R/W R CYRF69103 R/W R/W R R/W R/W R Page [+] Feedback ...
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... ACBE ACBF ACC0 running counter Document #: 001-07611 Rev * R 12-bit programmable timer load timing 16-bit free running counter loading timing CYRF69103 Prog Interval[11:8] R/W R/W R Page [+] Feedback ...
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... It simply prevents a posted interrupt from becoming pending. Nested interrupts can be accomplished by reenabling interrupts inside an interrupt service routine this, set the IE bit in the Flag Register. A block diagram of the CYRF69103 Interrupt Controller is shown in Figure 21-1. CYRF69103 Name 0040h ...
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... When an INT_CLRx register is read, any bits that are set indicates an interrupt has been posted for that hardware resource. Therefore, reading these registers gives the user the ability to determine all posted interrupts. CYRF69103 Interrupt Vector Interrupt Request M8C Core ...
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... Document #: 001-07611 Rev * INT1 GPIO Port 0 SPI Receive SPI Transmit R/W R/W R Program- mable Interrupt R/W – – Reserved GPIO Port2 Reserved - R/W – CYRF69103 Reserved POR/LVD R/W R/W R Reserved – – – INT2 16-bit Reserved Counter Wrap R/W R Page [+] Feedback ...
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... Unmask 16-bit Counter Wrap interrupt Bit 0: Reserved The GPIO interrupts are edge-triggered. Document #: 001-07611 Rev * Reserved – – – Reserved GPIO Port 2 Reserved Int Enable - R/W – CYRF69103 – – – INT2 16-bit Reserved Int Enable Counter Wrap Int Enable R/W R Page [+] Feedback ...
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... Unmask POR/LVD interrupt Document #: 001-07611 Rev * Timer Int Enable R/W – – INT1 GPIO Port 0 SPI Receive Int Enable Int Enable Int Enable R/W R/W R CYRF69103 Reserved – – – SPI Transmit Reserved POR/LVD Int Enable Int Enable R/W R/W R Page [+] Feedback ...
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... ITMRCLK Divider Gain[4:0] 32 kHz Bias Trim [1:0] 32 kHz Freq Trim [3:0] SPIData[7:0] Comm Mode CPOL CPHA INT1 GPIO Port 0 SPI Receive SPI Transmit 1 ms Timer Reserved Reserved GPIO Port 2 Reserved INT2 CYRF69103 R/W R/W R R/W Default P0.1 Reserved b--bb-b- 00000000 P1.1 P1 ...
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... X[7:0] Program Counter [7:0] Program Counter [15:8] Stack Pointer [7:0] XIO Super Carry WDRS PORS Sleep Reserved No Buzz Sleep Timer [1:0] PORLEV[1:0] Reserved Reserved Reserved CYRF69103 1 0 R/W Default r------- 00000000 16-bit Reserved ---b-bb- 00000000 Counter Wrap Int Enable Reserved POR/LVD bbbbbb-b ...
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... RSVD ABORT EN RSVD RSVD RSVD AUTO_CAL_TIME AUTO_CAL_OFFSET RSVD RSVD RSVD RSVD RSVD TX Buffer File RX Buffer File SOP Code File Data Code File Preamble File MFG ID File CYRF69103 [ Default Access -1001000 -bbbbbbb 00000000 bbbbbbbb TXC TXE 00000011 bbbbbbbb IRQEN IRQEN --000101 --bbbbbb ...
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... 2-way, 4 bytes/10 ms CPU speed = 6 MHz 2-way, 4 bytes/10 ms CPU speed = 6 MHz V = 3.0V, MCU sleep, PMU CC disabled V = 3.0V, MCU sleep, PMU enabled CC to inputs through a series resistor limiting input current to 1 mA. AC timing not guaranteed. CYRF69103 [12] ......................... >2000V [12] ................................ 1100V Min Typ Max Unit 1.8 3 ...
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... CPU speed = 6 MHz CPU speed = 3 MHz –100.0 µ –2 2 < V < except XTAL BIAS Low to High edge High to Low edge High to low edge [16] OL1 [16 OL1 OL2 CYRF69103 Min Typ Max Unit 1.1 mA 8.6 mA 21.2 mA 28.5 mA 39.9 mA 18 5 – 0 – 0 ...
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... Low for CPOL = 0, High for CPOL = 1 SCK to data valid Time before leading SCK edge SCK to data valid Time after SS LOW to data valid Before first SCK edge After last SCK edge Figure 25-1. Clock Timing T CYC CYRF69103 Min Typ Max Unit 26.4 MHz 50.0 kHz 2 MHz 2 ...
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... SCK (CPOL=0) T SCKH SCK (CPOL=1) T MDO MOSI MISO MSB T MSU Document #: 001-07611 Rev *F Figure 25-2. GPIO Timing Diagram T T R_GPIO Figure 25-3. SPI Master Timing, CPHA = 1 (SS is under firmware control in SPI Master mode) T SCKL MSB T MHD CYRF69103 F_GPIO LSB LSB Page [+] Feedback ...
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... T T MSU MHD Document #: 001-07611 Rev *F Figure 25-4. SPI Slave Timing, CPHA = 1 T SCKL MSB T SSU SHD MSB Figure 25-5. SPI Master Timing, CPHA = 0 (SS is under firmware control in SPI Master mode) T SCKL T MDO CYRF69103 T SSH LSB LSB LSB LSB Page [+] Feedback ...
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... SS T SSS SCK (CPOL=0) T SCKH SCK (CPOL=1) MSB MOSI T T SSU SHD T SDO1 MISO MSB Document #: 001-07611 Rev *F Figure 25-6. SPI Slave Timing, CPHA = 0 T SCKL T SDO CYRF69103 T SSH LSB LSB Page [+] Feedback ...
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... MHz 100 kHz ResBW 100 kHz ResBW 100 kHz ResBW seven steps, monotonic PN Code Pattern 10101010 PN Code Pattern 11110000 >0 dBm –6 dBc, 100 kHz ResBW CYRF69103 Min Typ Max Unit 2.400 2.497 GHz –97 dBm –93 dBm –80 –87 dBm – ...
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... Slow channels Medium channels Fast channels GFSK 250 kbps 125 kbps <125 kbps < 60 ppm crystal-to-crystal all modes except 64-DDR and 64-SDR < 60 ppm crystal-to-crystal 64-DDR and 64-SDR CYRF69103 Typ Max Unit –38 dBm –44 dBm –38 dBm –34 dBm –47 dBm – ...
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... Table 28-1. Package Handling Parameter Description T Bake Temperature BAKETEMP T Bake Time BAKETIME 29. Package Diagram Document #: 001-07611 Rev *F Ordering Part Number CYRF69103-40LFXC Min Typ 125 see package label Figure 29-1. 40-Pin Pb-Free QFN 6x6 mm CYRF69103 Max Unit see package label °C 72 hours ...
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... Document History Page Document Title: CYRF69103 Programmable Radio on Chip Low Power Document #: 001-07611 Orig. of Submission REV. ECN No. Change Date ** 479801 OYR See ECN *A 501282 OYR See ECN *B 631696 BOO See ECN *C 2447906 AESA See ECN *D 2615458 KKU/AESA 01/13/2009 Replaced 51-85190 with 001-12917. Fixed format and language inconsistencies. ...
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... I C Standard Specification as defined by Philips. As from October 1st, 2006 Philips Semiconductors has a new trade name - NXP Semiconductors. All products and company names mentioned in this document may be the trademarks of their respective holders. cypress.com/go/plc Revised February 26, 2010 CYRF69103 PSoC Solutions psoc.cypress.com/solutions PSoC 1 | ...