CYRF69103-40LFXC Cypress Semiconductor Corp, CYRF69103-40LFXC Datasheet - Page 28

• Manufacturer Part Number: CYRF69103-40LFXC
• Description: IC PROC 8K FLASH 40VQFN
• Manufacturer: Cypress Semiconductor Corp
• Series: CYRFr

Specifications of CYRF69103-40LFXC

• Package / Case: 40-VQFN Exposed Pad, 40-HVQFN, 40-SQFN, 40-DHVQFN
• Frequency: 2.4GHz
• Data Rate - Maximum: 1Mbps
• Modulation Or Protocol: ISM
• Applications: General Purpose
• Power - Output: 6dBm
• Sensitivity: -87dBm
• Voltage - Supply: 1.8 V ~ 3.6 V
• Current - Receiving: 21.9mA
• Current - Transmitting: 39.9mA
• Data Interface: PCB, Surface Mount
• Memory Size: 8kB Flash, 256B SRAM
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: 0°C ~ 70°C
• Processor Series: CYRF691x
• Core: M8C
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: SPI
• Maximum Clock Frequency: 2 MHz
• Number Of Programmable I/os: 15
• Number Of Timers: 4
• Operating Supply Voltage: 2.5 V, 3.3 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Program Memory Type: Flash
• Program Memory Size: 8 KB
• Operating Temperature (min): 0C
• Operating Temperature (max): 70C
• Operating Temperature Classification: Commercial
• Operating Supply Voltage (min): 1.8V
• Operating Supply Voltage (typ): 2.5/3.3V
• Operating Supply Voltage (max): 3.6V
• Height: 1 mm
• Length: 5.9 mm
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 1.8 V
• Width: 5.9 mm
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 770-1001 - ISP 4PORT CYPRESS ENCORE II MCU
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 428-1933

Table 15-4. Timer Clock Config (TMRCLKCR) [0x31] [R/W]
15.2.1 Interval Timer Clock (ITMRCLK)
The Interval Timer clock (ITMRCLK) can be sourced from the
internal 24 MHz oscillator, internal 32 kHz low power oscillator,
or timer capture clock. A programmable prescaler of 1, 2, 3, or 4
then divides the selected source. The 12-bit Programmable
Interval Timer is a simple down counter with a programmable
reload value. It provides a 1 μs resolution by default. When the
down counter reaches zero, the next clock is spent reloading.
The reload value can be read and written while the counter is
running, but care must be taken to ensure that the counter does
not unintentionally reload while the 12-bit reload value is only
partially stored—for example, between the two writes of the
12-bit value. The programmable interval timer generates
interrupt to the CPU on each reload.
The parameters to be set appears on the device editor view of
PSoC Designer after you place the CYRF69103 timer user
module.
PITIMER_Divider. The PITIMER_Source is the clock to the timer
and the PITIMER_Divider is the value the clock is divided by.
Document #: 001-07611 Rev *F
Bits 7:6
Bits 5:4
Note The 1024 μs interval timer is based on the assumption that TCAPCLK is running at 4 MHz. Changes in TCAPCLK frequency
cause a corresponding change in the 1024 μs interval timer frequency.
Bits 3:2
Bits 1:0
Note Changing the source of TMRCLK requires that both the source and destination clocks be running. Attempting to change
the clock source away from TCAPCLK after that clock has been stopped is not successful.
Bit #
Field
Read/Write
Default
The
TCAPCLK Divider [1:0]
TCAPCLK Divider controls the TCAPCLK divisor.
0 0 = Divider Value 2
0 1 = Divider Value 4
1 0 = Divider Value 6
1 1 = Divider Value 8
TCAPCLK Select
The TCAPCLK Select field controls the source of the TCAPCLK.
0 0 = Internal 24 MHz Oscillator
0 1 =Reserved
1 0 = Internal 32 kHz Low power Oscillator
1 1 = TCAPCLK Disabled
ITMRCLK Divider
ITMRCLK Divider controls the ITMRCLK divisor
0 0 = Divider value of 1
0 1 = Divider value of 2
1 0 = Divider value of 3
1 1 = Divider value of 4
ITMRCLK Select
0 0 = Internal 24 MHz Oscillator
0 1 = Reserved
1 0 = Internal 32 kHz Low power Oscillator
1 1 = TCAPCLK
parameters
R/W
TCAPCLK Divider
7
1
are
R/W
6
0
PITIMER_Source
R/W
TCAPCLK Select
5
0
and
R/W
4
0
The interval register (PITMR) holds the value that is loaded into
the PIT counter on terminal count. The PIT counter is a down
counter.
The Programmable Interval Timer resolution is configurable. For
example:
TCAPCLK divide by x of CPU clock (for example TCAPCLK
divide by 2 of a 24 MHz CPU clock gives a frequency of 12 MHz)
ITMRCLK divide by x of TCAPCLK (for example, ITMRCLK
divide by 3 of TCAPCLK is 4 MHz so resolution is 0.25 μs).
15.2.2 Timer Capture Clock (TCAPCLK)
The Timer Capture clock (TCAPCLK) can be sourced from the
internal 24 MHz oscillator or the internal 32 kHz low power oscil-
lator. A programmable prescaler of 2, 4, 6, or 8 then divides the
selected source.
R/W
ITMRCLK Divider
3
1
R/W
2
1
R/W
ITMRCLK Select
1
1
CYRF69103
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