AT86RF230-ZUR Atmel, AT86RF230-ZUR Datasheet - Page 20

• Manufacturer Part Number: AT86RF230-ZUR
• Description: TXRX LOW POWER 2.4GHZ 32VQFN
• Manufacturer: Atmel

Specifications of AT86RF230-ZUR

• Frequency: 2.4GHz
• Modulation Or Protocol: 802.15.4 Zigbee, 6LoWPAN, RF4CE, SP100, WirelessHART™, ISM
• Applications: Industrial Monitoring and Control, Wireless Alarm and Security Systems
• Power - Output: -17dBm ~ 3dBm
• Sensitivity: -101dBm
• Voltage - Supply: 1.8 V ~ 3.6 V
• Current - Receiving: 15.5mA
• Current - Transmitting: 16.5mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad, 32-HVQFN, 32-SQFN, 32-DHVQFN
• Number Of Receivers: 1
• Number Of Transmitters: 1
• Wireless Frequency: 2405 MHz to 2480 MHz
• Interface Type: SPI
• Noise Figure: 6 dB
• Output Power: 20 dB
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Maximum Supply Current: 16.5 mA
• Minimum Operating Temperature: - 40 C
• Modulation: OQPSK
• Protocol Supported: 802.15.4
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 1.8V
• Operating Supply Voltage (typ): 3V
• Operating Supply Voltage (max): 3.6V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Memory Size: -
• Data Rate - Maximum: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

6.5.2 Register Description
20
AT86RF230
Bit
0x0E
Read/Write
Reset value
Bit
0x0E
Read/Write
Reset value
Bit
0x0F
Read/Write
Reset value
Bit
0x0F
Read/Write
Reset value
Register 0x0E (IRQ_MASK)
The IRQ_MASK register is used to enable (set register bit to 1) or disable (set register
bit to 0) interrupt events by writing the corresponding bit to the interrupt mask register.
If an interrupt will be enabled or disabled, it is recommended to read the interrupt status
register 0x0F (IRQ_STATUS) first to clear the history.
Register 0x0F (IRQ_STATUS)
The IRQ_STATUS register contains the status of the individual interrupts. A read
access to this register resets all interrupt bits.
By reading the register after an interrupt is signaled at IRQ pin, the reason for the
interrupt can be identified.
A detailed description of the individual interrupts can be found in Table 6-8.
MASK_BAT_LOW MASK_TRX_UR
MASK_TRX_END MASK_RX_START MASK_PLL_UNLOCK MASK_PLL_LOCK
BAT_LOW
TRX_END
R/W
R/W
R
R
7
1
3
1
7
0
3
0
RX_START
TRX_UR
R/W
R/W
R
R
6
1
2
1
6
0
2
0
PLL_UNLOCK
R/W
R/W
R
R
5
1
1
1
5
0
1
0
Reserved
Reserved
PLL_LOCK
R/W
R/W
R
R
4
1
0
1
4
0
0
0
5131E-MCU Wireless-02/09
IRQ_STATUS
IRQ_STATUS
IRQ_MASK
IRQ_MASK