MFRC52201HN1,151 NXP Semiconductors, MFRC52201HN1,151 Datasheet - Page 11
MFRC52201HN1,151
Manufacturer Part Number
MFRC52201HN1,151
Description
IC READER 13.56MHZ 32-HVQFN
Manufacturer
NXP Semiconductors
Datasheet
1.MFRC52201HN1157.pdf
(109 pages)
Specifications of MFRC52201HN1,151
Rf Type
Read / Write
Frequency
13.56MHz
Package / Case
32-VQFN Exposed Pad, 32-HVQFN, 32-SQFN, 32-DHVQFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
935280547151
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9. MFRC522 Register SET
112132
Product data sheet
9.1 MFRC522 Registers Overview
Table 5:
Addr
(hex)
Page 0: Command and Status
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
Page 1: Command
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
Page 2: CFG
0
Register Name
Reserved
CommandReg
ComlEnReg
DivlEnReg
ComIrqReg
DivIrqReg
ErrorReg
Status1Reg
Status2Reg
FIFODataReg
FIFOLevelReg
WaterLevelReg
ControlReg
BitFramingReg
CollReg
Reserved
Reserved
ModeReg
TxModeReg
RxModeReg
TxControlReg
TxASKReg
TxSelReg
RxSelReg
RxThresholdReg Selects thresholds for the bit decoder
DemodReg
Reserved
Reserved
MfTxReg
MfRxReg
Reserved
SerialSpeedReg
Reserved
MFRC522 Registers Overview
Rev. 3.2 — 22 May 2007
Function
Reserved for future use
Starts and stops command execution
Controls bits to enable and disable the passing of Interrupt Requests
Controls bits to enable and disable the passing of Interrupt Requests
Contains Interrupt Request bits
Contains Interrupt Request bits
Error bits showing the error status of the last command executed
Contains status bits for communication
Contains status bits of the receiver and transmitter
In- and output of 64 byte FIFO buffer
Indicates the number of bytes stored in the FIFO
Defines the level for FIFO under- and overflow warning
Contains miscellaneous Control Registers
Adjustments for bit oriented frames
Bit position of the first bit collision detected on the RF-interface
Reserved for future use
Reserved for future use
Defines general modes for transmitting and receiving
Defines the transmission data rate and framing
Defines the receive data rate and framing
Controls the logical behavior of the antenna driver pins TX1 and TX2
Controls the setting of the TX modulation
Selects the internal sources for the antenna driver
Selects internal receiver settings
Defines demodulator settings
Reserved for future use
Reserved for future use
Controls some MIFARE
Controls some MIFARE
Reserved for future use
Selects the speed of the serial UART interface
Reserved for future use
®
®
communication transmit parameters
communication receive parameters
Contactless Reader IC
MFRC522
© NXP B.V. 2007. All rights reserved.
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