PIC18LF24K22-I/SS Microchip Technology, PIC18LF24K22-I/SS Datasheet - Page 287

• Manufacturer Part Number: PIC18LF24K22-I/SS
• Description: IC PIC MCU 16KB FLASH 28SSOP
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18LF24K22-I/SS

• Core Size: 8-Bit
• Program Memory Size: 16KB (8K x 16)
• Core Processor: PIC
• Speed: 64MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 19x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-SSOP (0.200", 5.30mm Width)
• Controller Family/series: PIC18
• No. Of I/o's: 25
• Eeprom Memory Size: 256Byte
• Ram Memory Size: 768Byte
• Cpu Speed: 64MHz
• No. Of Timers: 7
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

FIGURE 16-12:
TABLE 16-8:
 2010 Microchip Technology Inc.
BAUDCON1
BAUDCON2
INTCON
IPR1
IPR3
PIE1
PIE3
PIR1
PIR3
PMD0
RCREG1
RCSTA1
RCREG2
RCSTA2
SPBRG1
SPBRGH1
SPBRG2
SPBRGH2
TXSTA1
TXSTA2
Legend:
TXx/CKx pin
TXx/CKx pin
(SCKP = 0)
(SCKP = 1)
(Interrupt)
Note:
RXx/DTx
RCxIF bit
CREN bit
RCREGx
SREN bit
bit SREN
Name
Write to
Read
pin
Timing diagram demonstrates Sync Master mode with bit SREN = 1 and bit BRGH = 0.
— = unimplemented locations, read as ‘0’. Shaded bits are not used for synchronous master reception.
‘0’
UART2MD UART1MD TMR6MD TMR5MD
GIE/GIEH PEIE/GIEL TMR0IE
ABDOVF
ABDOVF
SSP2IP
SSP2IE
SSP2IF
SPEN
SPEN
CSRC
CSRC
Bit 7
REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION
—
—
—
SYNCHRONOUS RECEPTION (MASTER MODE, SREN)
bit 0
BCL2IP
BCL2IE
BCL2IF
RCIDL
RCIDL
ADIP
ADIE
Bit 6
ADIF
RX9
RX9
TX9
TX9
bit 1
DTRXP
DTRXP
EUSART1 Baud Rate Generator, High Byte
EUSART2 Baud Rate Generator, High Byte
EUSART1 Baud Rate Generator, Low Byte
EUSART2 Baud Rate Generator, Low Byte
RC1IP
RC2IP
RC1IE
RC2IE
RC1IF
RC2IF
SREN
SREN
TXEN
TXEN
Bit 5
EUSART1 Receive Register
EUSART2 Receive Register
bit 2
Preliminary
CKTXP
CKTXP
INT0IE
TX1IP
TX2IP
TX1IE
TX2IE
CREN
CREN
SYNC
SYNC
TX1IF
TX2IF
Bit 4
bit 3
TMR4MD
CTMUIP
CTMUIE
CTMUIF
SSP1IP
SSP1IE
SSP1IF
ADDEN
ADDEN
SENDB
SENDB
BRG16
BRG16
RBIE
Bit 3
PIC18(L)F2X/4XK22
bit 4
TMR5GIP
TMR5GIE
TMR5GIF
TMR3MD
TMR0IF
CCP1IP
CCP1IE
CCP1IF
BRGH
BRGH
FERR
FERR
Bit 2
—
—
bit 5
TMR3GIP TMR1GIP
TMR3GIE TMR1GIE
TMR3GIF TMR1GIF
TMR2MD
TMR2IP
TMR2IE
TMR2IF
INT0IF
OERR
OERR
TRMT
TRMT
WUE
WUE
Bit 1
bit 6
TMR1MD
bit 7
TMR1IP
TMR1IE
TMR1IF
ABDEN
ABDEN
RX9D
RX9D
TX9D
TX9D
RBIF
Bit 0
DS41412D-page 287
Register
on Page
274
274
115
127
129
123
125
118
120
273
273
272
272
56
—
—
—
—
—
—
‘0’