PIC18LF24K22-I/SS Microchip Technology, PIC18LF24K22-I/SS Datasheet - Page 52

• Manufacturer Part Number: PIC18LF24K22-I/SS
• Description: IC PIC MCU 16KB FLASH 28SSOP
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18LF24K22-I/SS

• Core Size: 8-Bit
• Program Memory Size: 16KB (8K x 16)
• Core Processor: PIC
• Speed: 64MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 19x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-SSOP (0.200", 5.30mm Width)
• Controller Family/series: PIC18
• No. Of I/o's: 25
• Eeprom Memory Size: 256Byte
• Ram Memory Size: 768Byte
• Cpu Speed: 64MHz
• No. Of Timers: 7
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIC18(L)F2X/4XK22
FIGURE 3-5:
3.4.1
This mode is unique among the three low-power Idle
modes, in that it does not disable the primary device
clock. For timing sensitive applications, this allows for
the fastest resumption of device operation with its more
accurate primary clock source, since the clock source
does not have to “warm-up” or transition from another
oscillator.
PRI_IDLE mode is entered from PRI_RUN mode by
setting the IDLEN bit and executing a SLEEP instruc-
tion. If the device is in another Run mode, set IDLEN
first, then clear the SCS bits and execute SLEEP.
Although the CPU is disabled, the peripherals continue
to be clocked from the primary clock source specified
by the FOSC<3:0> Configuration bits. The OSTS bit
remains set (see
When a wake event occurs, the CPU is clocked from the
primary clock source. A delay of interval T
required between the wake event and when code
execution starts. This is required to allow the CPU to
become ready to execute instructions. After the wake-
up, the OSTS bit remains set. The IDLEN and SCS bits
are not affected by the wake-up (see
FIGURE 3-6:
DS41412D-page 52
CPU Clock
Note1: T
PLL Clock
Peripheral
CPU Clock
Peripheral
Program
Counter
Program
Counter
Output
OSC1
Clock
OSC1
Clock
PRI_IDLE MODE
OST
Figure
= 1024 T
Q1
Wake Event
TRANSITION TIMING FOR WAKE FROM SLEEP (HSPLL)
TRANSITION TIMING FOR ENTRY TO IDLE MODE
3-6).
OSC
; T
Q1
Q2
PLL
T
OST
PC
= 2 ms (approx). These intervals are not shown to scale.
(1)
Q3
Figure
PC
T
3-7).
Q4
PLL
OSTS bit set
(1)
CSD
Preliminary
Q1
is
Q2 Q3 Q4 Q1 Q2
PC + 2
3.4.2
In SEC_IDLE mode, the CPU is disabled but the
peripherals continue to be clocked from the SOSC
oscillator. This mode is entered from SEC_RUN by set-
ting the IDLEN bit and executing a SLEEP instruction. If
the device is in another Run mode, set the IDLEN bit
first, then set the SCS<1:0> bits to ‘01’ and execute
SLEEP. When the clock source is switched to the SOSC
oscillator, the primary oscillator is shut down, the OSTS
bit is cleared and the SOSCRUN bit is set.
When a wake event occurs, the peripherals continue to
be clocked from the SOSC oscillator. After an interval
of T
cuting code being clocked by the SOSC oscillator. The
IDLEN and SCS bits are not affected by the wake-up;
the SOSC oscillator continues to run (see
Note:
CSD
PC + 2
following the wake event, the CPU begins exe-
Q3 Q4 Q1 Q2
SEC_IDLE MODE
The SOSC oscillator should already be
running prior to entering SEC_IDLE
mode. At least one of the secondary oscil-
lator enable bits (SOSCGO, T1SOSCEN,
T3SOSCEN or T5SOSCEN) must be set
when the SLEEP instruction is executed.
Otherwise, the main system clock will con-
tinue to operate in the previously selected
mode and the corresponding IDLE mode
will be entered (i.e., PRI_IDLE or
RC_IDLE).
PC + 4
Q3 Q4
 2010 Microchip Technology Inc.
Q1 Q2 Q3 Q4
PC + 6
Figure
3-7).