PIC18F26K22-I/SO Microchip Technology, PIC18F26K22-I/SO Datasheet - Page 171
![IC PIC MCU 64KB FLASH 28SOIC](/photos/28/69/286927/28-soic_m28b_sml.jpg)
PIC18F26K22-I/SO
Manufacturer Part Number
PIC18F26K22-I/SO
Description
IC PIC MCU 64KB FLASH 28SOIC
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Datasheets
1.PIC16F722-ISS.pdf
(8 pages)
2.PIC18F26J13-ISS.pdf
(496 pages)
3.PIC18F24K22-ISP.pdf
(494 pages)
Specifications of PIC18F26K22-I/SO
Core Size
8-Bit
Program Memory Size
64KB (32K x 16)
Core Processor
PIC
Speed
64MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
24
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
3.8K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 19x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-SOIC (0.300", 7.50mm Width)
Controller Family/series
PIC18
No. Of I/o's
25
Eeprom Memory Size
1KB
Ram Memory Size
3896Byte
Cpu Speed
64MHz
No. Of Timers
7
Processor Series
PIC18F
Core
PIC
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18F26K22-I/SO
Manufacturer:
NXP
Quantity:
928
Part Number:
PIC18F26K22-I/SO
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
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FIGURE 12-7:
12.12 Peripheral Module Disable
When a peripheral module is not used or inactive, the
module can be disabled by setting the Module Disable
bit in the PMD registers. This will reduce power con-
sumption to an absolute minimum. Setting the PMD
bits holds the module in Reset and disconnects the
module’s clock source. The Module Disable bits for
Timer1 (TMR1MD), Timer3 (TMR3MD) and Timer5
(TMR5MD) are in the PMD0 Register. See Section 3.0
“Power-Managed Modes” for more information.
2010 Microchip Technology Inc.
TIMER1/3/5
TMRxGIF
TMRxGE
TxGSPM
TxGPOL
TxGVAL
TxGGO/
TxG_IN
TxGTM
DONE
TxCKI
TIMER1/3/5 GATE SINGLE-PULSE AND TOGGLE COMBINED MODE
Cleared by software
N
Counting enabled on
rising edge of TxG
Set by software
Preliminary
N + 1
falling edge of TxGVAL
Set by hardware on
N + 2
PIC18(L)F2X/4XK22
N + 3
N + 4
Cleared by hardware on
falling edge of TxGVAL
DS41412A-page 171
Cleared by
software
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