PIC18F26K22-I/SO Microchip Technology, PIC18F26K22-I/SO Datasheet - Page 59
![IC PIC MCU 64KB FLASH 28SOIC](/photos/28/69/286927/28-soic_m28b_sml.jpg)
PIC18F26K22-I/SO
Manufacturer Part Number
PIC18F26K22-I/SO
Description
IC PIC MCU 64KB FLASH 28SOIC
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Datasheets
1.PIC16F722-ISS.pdf
(8 pages)
2.PIC18F26J13-ISS.pdf
(496 pages)
3.PIC18F24K22-ISP.pdf
(494 pages)
Specifications of PIC18F26K22-I/SO
Core Size
8-Bit
Program Memory Size
64KB (32K x 16)
Core Processor
PIC
Speed
64MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
24
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
3.8K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 19x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-SOIC (0.300", 7.50mm Width)
Controller Family/series
PIC18
No. Of I/o's
25
Eeprom Memory Size
1KB
Ram Memory Size
3896Byte
Cpu Speed
64MHz
No. Of Timers
7
Processor Series
PIC18F
Core
PIC
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18F26K22-I/SO
Manufacturer:
NXP
Quantity:
928
Part Number:
PIC18F26K22-I/SO
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
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4.0
The PIC18(L)F2X/4XK22 devices differentiate between
various kinds of Reset:
a)
b)
c)
d)
e)
f)
g)
h)
This section discusses Resets generated by MCLR,
POR and BOR and covers the operation of the various
start-up timers. Stack Reset events are covered in
Section 5.1.2.4 “Stack Full and Underflow Resets”.
WDT Resets are covered in Section 24.2 “Watchdog
Timer (WDT)”.
FIGURE 4-1:
2010 Microchip Technology Inc.
OSC1
MCLR
V
Note 1: See Table for time-out situations.
Power-on Reset (POR)
MCLR Reset during normal operation
MCLR Reset during power-managed modes
Watchdog Timer (WDT) Reset (during
execution)
Programmable Brown-out Reset (BOR)
RESET Instruction
Stack Full Reset
Stack Underflow Reset
DD
RESET
2: PWRT and OST counters are reset by POR and BOR. See Sections 4.3 and 4.4.
LFINTOSC
Instruction
RESET
OST/PWRT
Pointer
32 s
Stack
( )_IDLE
Brown-out
Time-out
Detect
Sleep
WDT
Reset
V
DD
OST
SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
PWRT
Stack Full/Underflow Reset
External Reset
MCLRE
10-bit Ripple Counter
11-bit Ripple Counter
(2)
BOREN
(2)
POR
1024 Cycles
65.5 ms
Preliminary
A simplified block diagram of the On-Chip Reset Circuit
is shown in Figure 4-1.
4.1
Device Reset events are tracked through the RCON
register (Register 4-1). The lower five bits of the
register indicate that a specific Reset event has
occurred. In most cases, these bits can only be cleared
by the event and must be set by the application after
the event. The state of these flag bits, taken together,
can be read to indicate the type of Reset that just
occurred. This is described in more detail in
Section 4.6 “Reset State of Registers”.
The RCON register also has control bits for setting
interrupt priority (IPEN) and software control of the
BOR (SBOREN). Interrupt priority is discussed in
Section 9.0
Section 4.4 “Brown-out Reset (BOR)”.
PIC18(L)F2X/4XK22
RCON Register
“Interrupts”.
S
R
BOR
DS41412A-page 59
Q
is
Enable OST
Enable PWRT
Chip_Reset
covered
(1)
in
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