XRD9836ACG Exar Corporation, XRD9836ACG Datasheet
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XRD9836ACG
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XRD9836ACG Summary of contents
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JUNE 2003 GENERAL DESCRIPTION The XRD9836 is a precision 16-bit analog front-end (AFE) for use in 3-channel/1-channel CCD/CIS docu- ment imaging applications. Pixel-by-pixel gain and offset for each of the 3 channels are controlled using a time multiplexed ...
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... XRD9836 16-BIT PIXEL GAIN AFE REV. 1.0 IGURE THE EVICE P N ART UMBER XRD9836ACG ADCLK 1 48 Dgnd VSAMP 2 47 Dvdd BSAMP 3 46 OGI [0] LCLMP 4 45 OGI [ OGI [2] SCLK 6 43 OGI [3] SDIO 7 42 OGI [4] LOAD 8 41 OGI [5] Ovdd 9 40 OGI [6] Ognd 10 39 ...
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PIN DESCRIPTIONS YMBOL 1 ADCLK 2 VSAMP 3 BSAMP 4 LCLMP SCLK 7 SDIO 8 LOAD 9 Ovdd 10 Ognd 11 Avdd 12 RED- 13 RED+ 14 GRN- 15 GRN+ ...
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XRD9836 16-BIT PIXEL GAIN AFE REV. 1.0.0 ELECTRICAL CHARACTERISTICS - XRD9836 Unless otherwise specified: AVDD=DVDD=3.3V, ADCLK = 30 MHz ARAMETER YMBOL Resolution R Fc3 Conversion Rate Fc1 Differential Non- DNL Linearity Input Referred ZSE Offset Offset Drift ...
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ELECTRICAL CHARACTERISTICS - XRD9836 (con’t) Unless otherwise specified: AVDD=DVDD=3.3V, ADCLK = 30 MHz ARAMETER YMBOL Input Voltage Range INVSR Input Leakage Iin Current Input Switch On Ron Resistance Input Switch Roff Off Resistance Internal Voltage ...
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XRD9836 16-BIT PIXEL GAIN AFE REV. 1.0.0 ELECTRICAL CHARACTERISTICS - XRD9836 (con’t) Unless otherwise specified: AVDD=DVDD=3.3V, ADCLK = 30 MHz ARAMETER YMBOL Gain Range Min. GRAN (Absolute Value) MIN Gain Range Max GRAN (Absolute Value) MAX Gain ...
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ELECTRICAL CHARACTERISTICS - XRD9836 (con’t) Unless otherwise specified: AVDD=DVDD=3.3V, ADCLK = 30 MHz ARAMETER YMBOL ADCLK tadclk3 Duty Cycle tadclk1 ADCLK period tcp1 (1-Ch mode) ADCLK period tcp3 (3-Ch mode) Single Channel tcr1 Conversion period ...
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XRD9836 16-BIT PIXEL GAIN AFE REV. 1.0.0 ELECTRICAL CHARACTERISTICS - XRD9836 (con’t) Unless otherwise specified: AVDD=DVDD=3.3V, ADCLK = 30 MHz ARAMETER YMBOL uSIO Data Setup Tuss Time uSIO Data Hold Time Tush uSIO Load Setup Tusls Time ...
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ELECTRICAL CHARACTERISTICS - XRD9836 (con’t) Unless otherwise specified: AVDD=DVDD=3.3V, ADCLK = 30 MHz ARAMETER YMBOL Analog IDD I AVDD Digital IDD I DVDD Output IDD I OVDD IDD Total I DD Power Dissipation P DISS ...
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XRD9836 16-BIT PIXEL GAIN AFE REV. 1.0.0 SYSTEM OVERVIEW The XRD9836 provides a 16-bit Analog Front End functionality for Mid-to-High range, next-generation scanner applications. It has 3 channels of Correlated Double Sampling (CDS), using a 10-bit Dynamic Off- set DAC, ...
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GAIN SELECT: The XRD9836’s Gain range is selectable to either with the Gain Select Bit. If Gain selected (Gain Select bit = 0), the maximum in- ...
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XRD9836 16-BIT PIXEL GAIN AFE REV. 1.0.0 have a range of +/- 128mV, with the ability to adjust PGA offsets to within +/- 0.25mV. There are two modes of operation for Pixel Gain and Offset control. The first is a ...
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In addition to the above requirement for LCLMP on a line by line basis there is an additional requirement for a one time LCLMP upon power-up to provide the AC coupling capacitor’s initial charge. The one time LCLMP ...
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XRD9836 16-BIT PIXEL GAIN AFE REV. 1.0.0 TIMING - CLOCK BASICS: The XRD9836 has 4 clock signals BSAMP, VSAMP, ADCLK and LCLMP. These inputs control the sam- pling, clamping and synchronization functions of the device. The pixel rate clocks are ...
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CCD Signal DelayB[7:4] BSAMP internal BSAMP VSAMP internal VSAMP ADCLK internal ADCLK ADCDO Output Bus F 11 & ADCDO (O IGURE IXEL IMING CCD Signal OGI Gain (n) Input Bus VSAMP internal OGI VSAMP ADCLK internal ...
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XRD9836 16-BIT PIXEL GAIN AFE REV. 1.0.0 ALTERNATE PIXEL OFFSET ADJUST MODE (APOAM): In some applications, alternate pixels along a scan line come from two different rows of CCD’s, causing a systematic offset between alternate pixels. When the XRD9836 is ...
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MICRO-CONTROLLER SERIAL PORT FOR MODE CONTROL (USIO): The uSIO is a bidirectional I/O port which is used for configuring various operating modes as well as phase aligning internal clocks (delay control). The serial port can be used to ...
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XRD9836 16-BIT PIXEL GAIN AFE REV. 1.0.0 ADDRESS RED RPGA [9] PGA GREEN GPGA [9] PGA BPGA BLUE 0 ...
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Red PGA D9 D8 Register RPGA RPGA RPGA [9] [8] (00000) default 0 0 RPGA[9:0] is used to set the gain of the Programmable Gain Amplifier (PGA) for the red channel. Code = 0000000000 is minimum gain. Code ...
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XRD9836 16-BIT PIXEL GAIN AFE REV. 1.0.0 Green Dynamic D9 D8 Offset Register GDOFF GDOFF GDOFF [9] [8] (00100) default 0 1 GDOFF[9:0] sets the course offset level prior to the PGA of the Green channel. Code = 0000000000 is ...
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Blue Fine D9 D8 Offset Register BF0FF BFOFF BFOFF [9] [8] (01000) default 1 0 BFOFF[9:0] sets the fine offset level after the PGA in the Blue channel. Code = 0000000000 is -128mV. Code =1111111111 is +128mV. Default ...
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XRD9836 16-BIT PIXEL GAIN AFE REV. 1.0.0 APOAM Red Fine D9 Offset Register ARFOF ARFOF [9] (01100) default 1 RFOFF[9:0] sets the fine offset level after the PGA of the Red channel for even pixels in APOAM Mode. The offset ...
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Control / Polarity D9 D8 Register CNTRL / POL (01111) default The CNTRL / POL register is used to program various options including: input timing polarity control, dynamic low power disable, power down for the chip, output enable, ...
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XRD9836 16-BIT PIXEL GAIN AFE REV. 1.0.0 Delay D9 Registers DelayA (10000) default DelayB (10001) default DelayC (10010) default DelayD (10011) default DelayA[7:4] - Controls the OGI_DLY. These bits are used to program the timing delay of the ADCLK used ...
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Mode D9 D8 Register MODES of operation (10100) default NOFS2 - No full scale divided by 2. Test Enable - Do not modify. Gain Select - Gain range is 1-10 for Gain Select = 0, and 2-20 for ...
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XRD9836 16-BIT PIXEL GAIN AFE REV. 1.0.0 TIMING DIAGRAMS CCDIN LCLMP ADCLK BSAMP VSAMP Clamp (Internal to XRD9836) F 17. 3-C IGURE HANNEL tap CCDIN LCLMP ADCLK tvfcr BSAMP tstl VSAMP Clamp (Internal to XRD9836) F 18. 1-C CDS M ...
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CIS ADCLK tstl tpwv F 19. 3-C CIS M IGURE HANNEL ODE tap CIS ADCCLK tstl VSAMP tpwv F 20. 1-C CIS M IGURE HANNEL ODE tcp3 tvfcr taclk3 taclk3 tcr3 (A ...
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XRD9836 16-BIT PIXEL GAIN AFE REV. 1.0.0 Pixel (n) GAIN & OFFSET ...
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APPLICATION NOTES AND SCHEMAT- ICS See Figure 23 for a typical CCD application hookup. The diagram shows an interface to a standard 3 channel output CCD. Both the ADC Output and OGI Control are parallel interfaces to the ...
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XRD9836 16-BIT PIXEL GAIN AFE REV. 1.0.0 115 VDD = 3. 30MHz 3-Channel Mode 105 25. XRD9836 T IDD IGURE YPICAL 2 1.5 1 0.5 0 -0.5 -1 -1.5 0 8192 F ...
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PACKAGE DRAWING: 16-BIT PIXEL GAIN AFE 31 XRD9836 REV. 1.0.0 ...
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... Products are not authorized for use in such applica- tions unless EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corpo- ration is adequately protected under the circumstances ...