XRD9836ACG Exar Corporation, XRD9836ACG Datasheet - Page 12

• Manufacturer Part Number: XRD9836ACG
• Description: IC 16B CCD/CIS SIG PROC 48TSSOP
• Manufacturer: Exar Corporation

Specifications of XRD9836ACG

• Package / Case: 48-TSSOP (0.240", 6.10mm Width)
• Number Of Bits: 16
• Number Of Channels: 3
• Power (watts): 500mW
• Voltage - Supply, Analog: 3 V ~ 3.6 V
• Voltage - Supply, Digital: 3 V ~ 3.6 V
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Contains lead / RoHS Compliant

XRD9836
16-BIT PIXEL GAIN AFE
REV. 1.0.0
have a range of +/- 128mV, with the ability to adjust
PGA offsets to within +/- 0.25mV.
There are two modes of operation for Pixel Gain and
Offset control. The first is a fixed gain and offset con-
trol mode where the gain and offset is adjusted once
per line or per scan. The second mode is a pixel to
pixel adjustment of gain and offset. This mode allows
for gain and offset adjustment for each and every pix-
el. These modes are controlled by bit D0, GOM (Gain
Offset Mode), in the MODE register.
In FGOM (Fixed Gain/Offset Mode, GOM=0), the us-
er can program the PGA gain, Dynamic and Fine Off-
set registers through the micro-controller serial inter-
face (uSIO).
In PPGOM (pixel-by-pixel gain and offset mode,
GOM=1), the user can input 10 bits of Gain and 10
bits of Dynamic offset data through the OGI port.
CCD MODE(CORRELATED DOUBLE
SAMPLING):
Correlated double sampling is a technique used to
level shift and acquire CCD output signals whose in-
formation is equal to the difference between consecu-
tive reference (V
The CDS process consists of three steps:
1) Sampling and holding the reference black level
(V
2) Sampling the video level (V
3) Subtracting the two samples to extract the video in-
formation. (CCD signal information = V
Once the CCD signal information has been extracted,
it can be processed further through amplification and/
or offset adjustment. Since system noise is also
stored and subtracted during the CDS process, sig-
nals with bandwidths less than half the sampling fre-
quency will be substantially attenuated.
F
IGURE
Black
).
CDS Signal
6. CDS
NC
CDS
Black
TO
ADC S
Dynamic
) and signal (V
10 BIT
Offset
DAC
+
IGNAL
10 Bit
PGA
Video
10 BIT
Offset
Fine
DAC
P
+
ATH
).
Video
MUX
Black
3:1
) samples.
- V
ADC
Video
)
12
LCLMP TIMING:
In order to reject higher frequency power supply
noise which is not attenuated near the sampling fre-
quency, the XRD9836 utilizes a fully differential input
structure. Since the CDS process uses AC coupled
inputs, the coupling capacitor must be charged to the
common-mode range of the analog front-end. This
can be accomplished by clamping the coupling ca-
pacitor to the internal clamp voltage when the CCD is
at a reference level at the beginning of each line us-
ing LCLMP. This needs to be done for enough clamp-
ing time (Tclamp) which is determined by external
Capacitor, internal switch resistance, BSAMP pulse
width and number of samples during line clamp. The
maximum capacitance is
where
The clamp LCLMP should be active for at least 4 pix-
els during Optical Black (OB) and should be inactive
during all of the Active portion of the line. Usually OB
lasts for 40 - 50 pixels. It is better if LCLMP remains
active during as much of OB as possible. LCLMP
should be set Active 1ns before BSAMP leading edge
and should be held for at least 1ns after BSAMP trail-
ing edge.
F
IGURE
Waveform
CCD O
CCD
7. CCD W
tpwb = clamp pulse width (BSAMP typ 25ns)
N = number of pixels used for clamping
Rc = clamp resistance (typ 50ohms)
Rs = signal source resistance (typ 50ohms)
Vr = black level
Vc = clamp voltage (1.2V)
Ve = error voltage (3.05uV worst case)
C
M A X
UTPUT
=
OB Pixels
V
Black
( Rc + R s ) * ln
AVEFORM
V
I
Dark
NFORMATION
N * t p w b
- D
EFINITION OF
Active Pixels
(
V
V
= (V
Black
Video
V r - V c
xr
xr
V e
BLACK
)
-V
T
ERMS
VIDEO
)