XRD9836ACG Exar Corporation, XRD9836ACG Datasheet - Page 17

• Manufacturer Part Number: XRD9836ACG
• Description: IC 16B CCD/CIS SIG PROC 48TSSOP
• Manufacturer: Exar Corporation

Specifications of XRD9836ACG

• Package / Case: 48-TSSOP (0.240", 6.10mm Width)
• Number Of Bits: 16
• Number Of Channels: 3
• Power (watts): 500mW
• Voltage - Supply, Analog: 3 V ~ 3.6 V
• Voltage - Supply, Digital: 3 V ~ 3.6 V
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Contains lead / RoHS Compliant

xr
xr
MICRO-CONTROLLER SERIAL PORT
FOR MODE CONTROL (USIO):
The uSIO is a bidirectional I/O port which is used for
configuring various operating modes as well as phase
aligning internal clocks (delay control). The serial port
can be used to program any of the registers listed in
the registers table. Note that SDIO is a bidirectional
pin used to read or write the XRD9836 internal regis-
ters. The R/W bit will define the direction of the bus
after Address bits. If R/W = 0, a write to the XRD9836
is performed. If R/W = 1, a read of the XRD9836’s in-
ternal registers is performed.
During a write operation there must be 18 positive
edges of SCLK between the fall of LOAD and the rise
of LOAD. If there are more or less than 18, the write
operation will not take place. For a write to the
F
F
IGURE
IGURE
15. S
16. S
SCLK
SCLK
LOAD
LOAD
SDIO
SDIO
Tusls
configured
Tusls
configured
ERIAL
ERIAL
SDIO
SDIO
as
as
P
P
Write
ORT
Read
ORT
R/W
R/W
Tuss
W
R
msb
A4
A4
msb
EAD
Register Address
Register Address
RITE
A3
A3
Input
T
T
IMING
A2
A2
IMING
A1
A1
(R/W=1)
(R/W=0)
A0
A0
lsb
lsb
Tusp
Tush
Tri-state
E1
Dummy
E1
Dummy
bits
bits
E0
E0
Tuss
17
msb
D9
msb
Input
XRD9836 the SDIO pin stays configured as an input
for entire 18 SCLK's before LOAD goes high. The E0
and E1 bits are dummy (unused) bits.
For a read of the XRD9836 internal registers (R/W=1)
the E0 and E1 are used as a transition time for the
SDIO pin going from an input to a output. During this
time SDIO pin is tri-stated. SDIO is an input while se-
rial port accepts the address of the register to be read
and during the E0 and E1 time period transitions to
an output for the read operation.
During a read operation the first 18 positive edges are
used. If there are less than 18, not all of the data will
be output. If there are more than 18, only the first 18
bits will be valid. The data becomes valid after the ris-
ing edge of SCLK.
Tusdvd
D9
D8
D8
D7
D7
Write Register Data
Read Register Data
D6
D6
D5
Output
D5
Tusp
Tush
D4
D4
D3
D3
D2
16-BIT PIXEL GAIN AFE
D2
D1
Tuslh
Tuslh
D1
lsb
lsb
D0
D0
XRD9836
REV. 1.0.0