XR17V258IV-F Exar Corporation, XR17V258IV-F Datasheet - Page 13
![IC UART PCI BUS OCTAL 144LQFP](/photos/29/6/290685/xr17v358_sml.jpg)
XR17V258IV-F
Manufacturer Part Number
XR17V258IV-F
Description
IC UART PCI BUS OCTAL 144LQFP
Manufacturer
Exar Corporation
Type
Octal UARTr
Datasheet
1.XR17V258IVTR-F.pdf
(69 pages)
Specifications of XR17V258IV-F
Number Of Channels
8
Package / Case
144-LQFP
Features
*
Fifo's
64 Byte
Protocol
RS485
Voltage - Supply
3.3V, 5V
With Auto Flow Control
Yes
With Irda Encoder/decoder
Yes
With False Start Bit Detection
Yes
With Modem Control
Yes
Mounting Type
Surface Mount
Data Rate
8 Mbps
Supply Voltage (max)
3.6 V
Supply Voltage (min)
3 V
Supply Current
4 mA
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 45 C
Mounting Style
SMD/SMT
Operating Supply Voltage
3 V to 3.6 V
No. Of Channels
8
Uart Features
Tx/Rx FIFO Counters
Supply Voltage Range
3V To 3.6V
Operating Temperature Range
-40°C To +85°C
Digital Ic Case Style
LQFP
No. Of Pins
144
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XR17V258IV-F
Manufacturer:
EXAR
Quantity:
295
Company:
Part Number:
XR17V258IV-F
Manufacturer:
Exar Corporation
Quantity:
10 000
Part Number:
XR17V258IV-F
Manufacturer:
EXAR/艾科嘉
Quantity:
20 000
REV. 1.0.2
D3
The V258 enters the state when power is removed from the device. All context is lost in this state and the V258
does not support PME# in this state. When power is restored, PCI RST# must be asserted and the V258 will
return to the D0 Uninitialized state with a full PCI 3.0 compliant power-on reset sequence. The V258 will set all
its registers and outputs to the power-on defaults just as at initial power up. The system software must then
fully initialize and re-configure the V258 to place it in the D0 Active state.
This 32-bit register can be used to store user information and is writable only via the EEPROM. This is
implemented at an offset of 0x48 in the PCI Configuration Space immediately following the Power
Management Registers. This register can be used to store application-specific information which may be used
by the device driver to initialize the device appropriately.
N
F
1.3
OTE
IGURE
A
COLD
O
DDRESS
0x48
FFSET
: EWR=Read/Write from external EEPROM.
S
4. P
Special Read/Write Register to store User Information
TATE
OWER
B
31:0
ITS
Active
S
Power on +
PCI RST#
TATE
D0
EWR
T
T
YPE
RANSITIONS OF THE
66MHZ PCI BUS OCTAL UART WITH POWER MANAGEMENT SUPPORT
T
ABLE
User Information Writable only through EEPROM
3: S
PECIAL
XR17V258
Uninitialized
D3
R
D0
13
EAD
hot
D
/W
ESCRIPTION
RITE
R
EGISTER
VCC Removed
Power on +
PCI RST#
D3
cold
XR17V258
R
0x00000000
ESET
(
HEX
V
ALUE
)