xr17v258 Exar Corporation, xr17v258 Datasheet
xr17v258
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xr17v258 Summary of contents
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... PCI BUS OCTAL UART WITH POWER MANAGEMENT SUPPORT NOVEMBER 2005 GENERAL DESCRIPTION 1 The XR17V258 (V258 single chip 8-channel 66MHz PCI (Peripheral Component Interconnect) UART (Universal Asynchronous Transmitter) solution, optimized performance and lower power. The V258 device with its fifth generation register set is designed to meet the ...
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... VCC 138 AD31 AD30 139 140 AD29 AD28 141 AD27 142 AD26 143 144 AD25 ORDERING INFORMATION ART UMBER ACKAGE XR17V258IV 144-Lead LQFP XR17V258 PERATING EMPERATURE ANGE -40°C to +85° REV. 1.0.0 72 CTS5# 71 RX5 ENIR 70 69 TMRCK 68 MPIO4 67 MPIO5 66 ...
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... Initialization device select (active HIGH). O Device select to the XR17V258 (active LOW). Device interrupt from XR17V258 (open drain, active LOW). Power Management Event signal. While the Power Management Control/Status Register is set, the V258 asserts the PME# upon receiving a new character or upon change of state of modem inputs on any channel ...
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... XR17V258 66MHZ PCI BUS OCTAL UART WITH POWER MANAGEMENT SUPPORT PIN DESCRIPTIONS AME IN DTR0# 126 DSR0# 130 CD0# 129 RI0# 128 TX1 117 RX1 124 RTS1# 119 CTS1# 123 DTR1# 118 DSR1# 122 CD1# 121 RI1# 120 TX2 106 RX2 ...
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... UART channel 6 Data Terminal Ready or general purpose output (active LOW). I UART channel 6 Data Set Ready or general purpose input (active LOW). I UART channel 6 Carrier Detect or general purpose input (active LOW). I UART channel 6 Ring Indicator or general purpose input (active LOW). O UART channel 7 Transmit Data or infrared transmit data. 5 XR17V258 D ESCRIPTION ...
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... XR17V258 66MHZ PCI BUS OCTAL UART WITH POWER MANAGEMENT SUPPORT PIN DESCRIPTIONS AME IN RX7 47 RTS7# 52 CTS7# 48 DTR7# 53 DSR7# 49 CD7# 50 RI7# 51 ANCILLARY SIGNALS MPIO0 108 I/O MPIO1 107 I/O MPIO2 74 I/O MPIO3 73 I/O MPIO4 68 I/O MPIO5 67 I/O MPIO6 66 I/O MPIO7 65 I/O EECK 116 EECS 115 EEDI 114 EEDO 113 ...
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... MCR bit [6] in the UART. Power supply for the UART core logic and PCI bus I/O - 3.3V only. The V258 is PCI 3.0 signalling compliant at 3.3V operation. The non-PCI inputs (except XTAL1) are 5V tolerant. This includes all the serial (modem) inputs. Power supply common, ground. 7 XR17V258 D ESCRIPTION ...
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... Xon/Xoff software flow control, programmable transmit and receive FIFO trigger level, FIFO level counters, infrared encoder and decoder (IrDA ver. 1.0), and a programmable fractional baud rate generator with a prescaler 4X, and data rate Mbps at 8X sampling clock.The XR17V258 is available in a 144-pin LQFP (20x20x1.4mm) industrial grade package. ...
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... REV. 1.0.0 1.0 XR17V258 INTERNAL REGISTERS The XR17V258 UART has three different sets of registers as shown in Configuration Space Registers are for plug-and-play auto-configuration when connecting the device to the PCI bus. This auto-configuration feature makes installation very easy into a PCI system and it is part of the PCI local bus specification ...
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... XR17V258 66MHZ PCI BUS OCTAL UART WITH POWER MANAGEMENT SUPPORT T 1: PCI L ABLE A DDRESS B T ITS YPE O FFSET 0x00 31:16 EWR Device ID (Exar device ID number) 15:0 EWR Vendor ID (Exar) specified by PCISIG 0x04 31 RWC Parity error detected. Cleared by writing a logic 1. 30 RWC System error detected. Cleared by writing a logic 1. ...
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... PME Support (PME# can be asserted from D3 Reserved or Not Supported PME Clock (PCI clock is required for PME# generation) Version Next Item Pointer Capability ID Unimplemented Data Register Unimplemented Bridge Support Extensions Power Management Control/Status Register (PMCSR) PME_Status Reserved 11 XR17V258 R EGISTERS R V ESET ALUE ( ) HEX OR BINARY 0x00000000 0x00000000 ...
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... D0 S TATE The XR17V258 must be placed in the D0 state before being used in a system. The D0 state represents two states - D0 Uninitalized and D0 Active. Upon entering D0 from power up or transition from the D0 Uninitialized state. Once initialized by the system software, the V258 will enter the D0 Active state. ...
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... B T ITS YPE O FFSET 0x48 31:0 EWR N : EWR=Read/Write from external EEPROM. OTE XR17V258 D0 Uninitialized VCC Removed D3 hot ABLE PECIAL EAD RITE EGISTER D ESCRIPTION User Information Writable only through EEPROM 13 XR17V258 Power on + PCI RST# D3 cold R V ESET ALUE ( ) HEX 0x00000000 ...
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... XR17V258 66MHZ PCI BUS OCTAL UART WITH POWER MANAGEMENT SUPPORT 1.4 EEPROM Interface The V258 provides an interface to an Electrically Erasable Programmable Read Only Memory (EEPROM). The EEPROM must be a 93C46-like device, with its memory configured as 16-bit words. This interface is provided in order to program the registers in the PCI Configuration Space of the PCI UART during power-up. The following table gives the mapping of the EEPROM memory to the registers in the V258’ ...
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... PCI BUS OCTAL UART WITH POWER MANAGEMENT SUPPORT REV. 1.0 XR17V258 UART ABLE FFSET DDRESS EMORY PACE 0x000 - 0x00F UART channel 0 Regs 0x010 - 0x07F Reserved 0x080 - 0x093 DEVICE CONFIGURA- TION REGISTERS 0x094 - 0x0FF Reserved 0x100 UART 0 – Read FIFO 0x100 UART 0 – ...
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... XR17V258 66MHZ PCI BUS OCTAL UART WITH POWER MANAGEMENT SUPPORT T 5: XR17V258 UART ABLE FFSET DDRESS EMORY PACE 0x800 - 0x80F UART channel 4 Regs 0x810 - 0x8FF Reserved 0x900 UART 4 – Read FIFO 0x900 UART 4 – Write FIFO 0x940 - 0x97F Reserved 0x980 - 0x9FF UART 4 – ...
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... Read-only Device revision Read-only Device identification Write-only Read/Write MPIO interrupt mask Read/Write MPIO level control Read/Write MPIO output control Read/Write MPIO input polarity select Read/Write MPIO select 17 XR17V258 BYTE ALIGNMENT RESET STATE Bits [7:0] = 0x00 Bits [7:0] = 0x00 Bits [7:0] = 0x00 Bits [7:0] = 0x00 Bits [7:0] = 0x00 ...
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... The Global Interrupt Register The XR17V258 has a 32-bit wide register [INT0, INT1, INT2 and INT3] to provide interrupt information and supports two interrupt schemes. The first scheme is an 8-bit indicator representing all 8 channels with each bit representing each channel from This permits the interrupt service routine to quickly determine which UART channels need servicing so that it can go to the appropriate UART channel interrupt service routines ...
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... MSR, RTS/CTS or DTR/DSR delta or Xoff/Xon det. or special char. detected 1 Reserved. 0 MPIO pin(s). Available only within channel 0, reserved in other channels. 1 TIMER Time-out. Available only within channel 0, reserved in other chan- nels. 9: UART C [7:0] I HANNEL NTERRUPT 19 XR17V258 INT1 Register Channel-1 Channel-0 Bit Bit Bit Bit Bit Bit Bit Bit N+1 ...
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... XX-XX-00-00) X The XR17V258 has a general purpose 16-bit timer/counter. The crystal/clock at the XTAL1 input or an external clock at the TMRCK input pin can be selected as the clock source for the timer/counter. The timer can be set single-shot for a one-time event or re-triggerable for a periodic signal. An interrupt may be generated when the timer times out and will show Channel 0 interrupt (see configuration registers [TIMERCNTL, TIMER, TIMELSB, TIMERMSB] ...
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... Timer has been started: Any write to TIMER MSB, LSB registers ■ Issue of any command other than ’Start Timer’, ’Stop Timer’ and ’Reset Timer’ ■ T 10: TIMER CONTROL R ABLE EGISTERS Figure 7 21 XR17V258 ). If the Timer times out, re-starting the ...
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... XR17V258 66MHZ PCI BUS OCTAL UART WITH POWER MANAGEMENT SUPPORT Timer Operation in Re-triggerable Mode: In the re-triggerable mode, when the Timer is started, the Timer output will stay HIGH until it reaches half of the terminal count clocks) and toggle LOW and stay LOW for a similar amount of time (Q clocks). The above step will keep repeating until the Timer is stopped at which time the output will become HIGH (default state) ...
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... Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0 Ch-7 LOW HOT AND E TRIGGERABLE Timer Timed TIMERCNTL Out read Timer Timed 8XMODE Register Ch-6 Ch-5 Ch-4 Ch-3 Ch-2 Ch-1 Ch-0 Table 21 for details. . RESET Register Individual UART Channel Reset Enable Ch-6 Ch-5 Ch-4 Ch-3 Ch-2 Ch-1 Ch-0 23 XR17V258 M ODES TIMERCNTL Timer Timed Out read Out ...
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... DVID register provides device identification. A return value of 0x48 from this register indicates the device is a XR17V258. The DREV register returns an 8-bit value of 0x01 for revision A with 0x02 equals to revision B and so on. This information is very useful to the software driver for identifying which device it is communicating with and to keep up with revision changes ...
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... Timer output, all the above 5 registers lose control over the MPIO[0] pin. For details on Timer output, please see “Section 1.6.2, General Purpose 16-bit Timer/Counter [TIMERMSB, TIMELSB, TIMER, TIMECNTL] (default 0xXX-XX-00-00)” on page 20 1.6.10 MPIO REGISTERS There are 5 registers that select, control and monitor the 8 multipurpose inputs and outputs. the internal circuitry XR17V258 Figure 9 shows ...
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... XR17V258 66MHZ PCI BUS OCTAL UART WITH POWER MANAGEMENT SUPPORT IGURE ULTIPURPOSE INPUT MPIOINT [7:0] INT AND MPIOLVL [7:0] Read Input Level MPIOINV [7:0] (Input Inversion Enable =1) MPIOLVL [7:0] (Output Level) MPIO3T [7:0] (3-state Enable =1) MPIOSEL [7:0] (Select Input=1, Output=0 ) MPIOINT [7:0] (default 0x00) The MPIOINT register enables the multipurpose input pin interrupt MPIO pin is selected by MPIOSEL as an input, then it can be selected to generate an interrupt ...
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... MPIO5 MPIO4 MPIO3 MPIO2 MPIO1 MPIO0 MPIOINV Register Multipurpose Input Signal Inversion Enable Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0 MPIO7 MPIO6 MPIO5 MPIO4 MPIO3 MPIO2 MPIO1 MPIO0 MPIOSEL Register Multipurpose Input/Output Selection MPIO6 MPIO5 MPIO4 MPIO3 MPIO2 MPIO1 MPIO0 27 XR17V258 page 31 for programming details. ...
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... FIFO DATA LOADING AND UNLOADING IN 32-BIT FORMAT. The XR17V258 supports PCI Burst Read and PCI Burst Write transactions anywhere in the mapped memory region (except reserved areas). In addition, to utilize this feature fully, the device provides a separate memory location (apart from the individual channel’s register set) where the RX and the TX FIFO can be read from/ ...
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... Special Rx FIFO Data Unloading at locations 0x180, 0x380, 0x580, and 0x780 The XR17V258 also provides the same RX FIFO data along with the LSR status information of each byte side- by-side, at locations 0x180 (channel 0), 0x380 (channel 1), 0x580 (channel 2), ....., 0xF80 (channel 3). The entire RX data along with the status can be downloaded in a single PCI Burst Read operation of 32 DWORD reads ...
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... XR17V258 66MHZ PCI BUS OCTAL UART WITH POWER MANAGEMENT SUPPORT 3.1.3 Tx FIFO Data Loading at locations 0x100, 0x300, 0x500, 0x700, 0x900, 0xB00, 0xD00, 0xF00 The TX FIFO data (up to the maximum 64 bytes) can be loaded in a single burst 32-bit write operation (maximum 16 DWORD writes) at memory locations 0x100 (channel 0), 0x300 (channel 1), 0x500 (channel 2), ...
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... Bit-6 Bit-5 Bit-4 Bit-3 Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-7 Bit-6 Bit-5 Bit-4 Bit XR17V258 , 16C550 COMPATIBLE Bit-2 Bit-1 Bit-0 Bit-2 Bit-1 Bit-0 Bit-2 Bit-1 Bit-0 Bit-2 Bit-1 Bit-0 Bit-2 Bit-1 Bit-0 Bit-2 Bit-1 Bit-0 ...
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... XR17V258 66MHZ PCI BUS OCTAL UART WITH POWER MANAGEMENT SUPPORT The closest divisor that is obtainable in the V258 can be calculated using the following formula: ROUND( (Required Divisor - TRUNC (Required Divisor) )*16)/16 + TRUNC (Required Divisor), where DLM = TRUNC( Required Divisor) >> 8 DLL = TRUNC (Required Divisor) & 0xFF ...
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... ALUE ALUE V258 12/ 8/ 11/ 8/ 12/ 4/ 10/ 8/16 0 Figure 12 below explains how it works. 33 XR17V258 16X S AMPLING DLD ROGRAM ROGRAM ATA RROR (HEX) V (HEX)) R (%) ALUE ATE ...
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... XR17V258 66MHZ PCI BUS OCTAL UART WITH POWER MANAGEMENT SUPPORT F 12. A RTS/DTR CTS/DSR F IGURE UTO AND Local UART UARTA Receiver FIFO Trigger Reached Auto RTS Trigger Level Transmitter Auto CTS Monitor Assert RTS# to Begin Transmission 1 RTSA# 2 CTSB# 3 TXB Data Starts 4 RXA FIFO ...
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... DSR#, CD# and RI# inputs are ignored RANSMIT ATA NCODING AND Character Data Bits Bit Time 3/16 Bit Time Bit Time 1/16 Clock Delay Data Bits Character 35 XR17V258 ECEIVE ATA ECODING 1 0 1/2 Bit Time IrEncoder IRdecoder- ...
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... XR17V258 66MHZ PCI BUS OCTAL UART WITH POWER MANAGEMENT SUPPORT F 14 IGURE NTERNAL OOP 4.5 UART CHANNEL CONFIGURATION REGISTERS AND ADDRESS DECODING The 8 sets of UART configuration registers are decoded using address lines A9 to A11 as shown below. Address lines select the 16 registers in each channel. The first 8 registers are 16550 compatible with EXAR enhanced feature registers located on the upper 8 addresses ...
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... OMPATIBLE Read-only Write-only Read/Write Read/Write Read/Write Read/Write Read-only Write-only Read/Write Read/Write Read-only Read-only Write-only Read/Write E R NHANCED EGISTER Read/Write Read/Write Read-only Write-only Read-only Write-only Write-only Read-only Write-only Write-only Write-only 37 XR17V258 C RITE OMMENTS LCR[ LCR[ LCR[ LCR[ LCR[ LCR[ Xon,Xoff Rcvd. Flags ...
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... XR17V258 66MHZ PCI BUS OCTAL UART WITH POWER MANAGEMENT SUPPORT T 14: UART CHANNEL CONFIGURATION REGISTERS DESCRIPTION. ABLE DDRESS EG EAD B [7] IT A3- AME RITE RHR R BIT [ THR W BIT [ DLL R/W BIT [ DLM R/W BIT [ ...
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... XON2 W Bit [ MCR bits [3:2] (OP1 and OP2 outputs) are not available in the XR17V258. They are present for 16C550 OTE compatibility during Internal loopback, see 4.6 Transmitter The transmitter section comprises bytes of FIFO, a byte-wide Transmit Holding Register (THR) and an 8-bit Transmit Shift Register (TSR) ...
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... XR17V258 66MHZ PCI BUS OCTAL UART WITH POWER MANAGEMENT SUPPORT F 15 IGURE RANSMITTER PERATION IN NON Data Byte 16X or 8X Clock (8XMODE Register) Transmit Shift Register (TSR) 4.6.3 Transmitter Operation in FIFO Mode The host may fill the transmit FIFO with bytes of transmit data. The THR empty flag (LSR bit [5]) is set whenever the FIFO is empty ...
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... FIFO trigger level (RXTRG). (64-byte) FIFO is Enable by FCR bit-0=1 RTS#/DTR# de-asserts when data fills above Data fills to 56 the trigger level to suspend remote transmitter. Enable by EFR bit-6=1, MCR bit-2. Receive Data 41 XR17V258 Receive Data Characters RXFIFO1 Receive Data Characters RXFIFO1 ...
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... XR17V258 66MHZ PCI BUS OCTAL UART WITH POWER MANAGEMENT SUPPORT 5.0 UART CONFIGURATION REGISTERS 5.1 Receive Holding Register (RHR) - Read only SEE”RECEIVER” ON PAGE 41. 5.2 Transmit Holding Register (THR) - Write only SEE”TRANSMITTER” ON PAGE 39. 5.3 Baud Rate Generator Divisors (DLM, DLL and DLD) The Baud Rate Generator (BRG) generates the data rate for the transmitter and receiver ...
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... ISR will give the user the current highest pending interrupt level to be serviced, others queue up for next service. No other interrupts are acknowledged until the pending interrupt is serviced. The Interrupt Source Table, Table 15 , shows the data values (bit [5:0]) for the six prioritized interrupt levels and the interrupt sources associated with each of these interrupt levels. 43 XR17V258 ...
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... XR17V258 66MHZ PCI BUS OCTAL UART WITH POWER MANAGEMENT SUPPORT 5.5.1 Interrupt Generation: • LSR is by any of the LSR bits [4:1]. See IER bit [2] description on the previous page. • RXRDY trigger level. • RXRDY Time-out 4-char plus 12 bits delay timer. • ...
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... FCR[0]: TX and RX FIFO Enable • Logic 0 = Disable the transmit and receive FIFO (default). • Logic 1 = Enable the transmit and receive FIFOs. This bit must be set to logic 1 when other FCR bits are written or they will not be programmed. below shows the selections. 45 XR17V258 ...
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... XR17V258 66MHZ PCI BUS OCTAL UART WITH POWER MANAGEMENT SUPPORT T 16: T ABLE RANSMIT AND T FCTR FCTR FCR RIGGER T BIT [7] BIT [6] BIT [7] ABLE Table Table Table Table 5.7 Line Control Register (LCR) - Read/Write The Line Control Register is used to specify the asynchronous data communication format ...
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... Force parity to mark, “1” Forced parity to space, “0” TOP BIT LENGTH ORD (B LENGTH IT TIME 0 5,6,7,8 1 (default 1-1/2 1 6,7,8 2 BIT [0] W ORD LENGTH (default XR17V258 P ARITY SELECTION No parity Odd parity Even parity ( )) S ...
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... XR17V258 66MHZ PCI BUS OCTAL UART WITH POWER MANAGEMENT SUPPORT 5.8 Modem Control Register (MCR) - Read/Write The MCR register is used for controlling the modem interface signals or general purpose inputs/outputs. MCR[7]: Clock Prescaler Select • Logic 0 = Divide by one. The input clock from the crystal or external clock is fed directly to the Programmable Baud Rate Generator without further modification, i.e., divide by one (default). • ...
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... LSR[2]: Receive Data Parity Error Flag • Logic parity error (default). • Logic 1 = Parity error. The receive character in RHR (top of the FIFO) does not have correct parity information and is suspect. This error is associated with the character available for reading in RHR. 49 XR17V258 ...
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... XR17V258 66MHZ PCI BUS OCTAL UART WITH POWER MANAGEMENT SUPPORT LSR[1]: Receiver Overrun Flag • Logic overrun error (default). • Logic 1 = Overrun error. A data overrun error condition occurred in the receive shift register. This happens when additional data arrives while the FIFO is full. In this case the previous data in the receive shift register is overwritten ...
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... ELAY XR17V258 RANSMIT TO ECEIVE ATA IT S IME ...
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... XR17V258 66MHZ PCI BUS OCTAL UART WITH POWER MANAGEMENT SUPPORT MSR [3]: Transmitter Disable This bit can be used to disable the transmitter by halting the Transmit Shift Register (TSR). When this bit is set to a logic 1, the bytes already in the FIFO will not be sent out. Also, any more data loaded into the FIFO will stay in the FIFO and will not be sent out ...
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... Table 20 ). When the Xon1 and Xon2 and Xoff1 and Xoff2 modes 53 XR17V258 Table ABLE IS ELECTED RTS/DTR H YSTERESIS [ CHARACTERS 0 +/- 4 +/- 6 +/- 8 +/- 8 +/- 16 +/- 24 +/- 32 +/- 12 +/- 20 +/- 28 +/- 36 +/- 40 +/- 44 +/- 48 +/- 52 ...
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... XR17V258 66MHZ PCI BUS OCTAL UART WITH POWER MANAGEMENT SUPPORT EFR[6]: Auto RTS or DTR Flow Control Enable RTS#/DTR# output may be used for hardware flow control by setting EFR bit [6] to logic 1. When Auto RTS/ DTR is selected, an interrupt will be generated when the receive FIFO is filled to the programmed trigger level and RTS/DTR# will de-assert (HIGH) at the next upper trigger or selected hysteresis level ...
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... Receiver compares Xon1 or Xon2, Xoff1 or Xoff2 1 1 Transmit Xon1 and Xon2, Xoff1 and Xoff2 Receiver compares Xon1 and Xon2, Xoff1 and Xoff2 transmit flow control Receiver compares Xon1 and Xon2, Xoff1 and Xoff2 55 XR17V258 ECEIVE OFTWARE LOW ONTROL ...
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... XR17V258 66MHZ PCI BUS OCTAL UART WITH POWER MANAGEMENT SUPPORT 5.20 XCHAR REGISTER, READ ONLY This register gives the status of the last sent control character (Xon or Xoff) and the last received control character (Xon or Xoff). This register will be reset to 0x00 if, at anytime, the Software Flow Control is disabled. ...
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... Bits [7:0] = 0x00 RFTRG Bits [7:0] = 0x00 XCHAR Bits [7:0] = 0x00 XON1 Bits [7:0] = 0x00 XON2 Bits [7:0] = 0x00 XOFF1 Bits [7:0] = 0x00 XOFF2 Bits [7:0] = 0x00 T 21: UART RESET CONDITIONS ABLE I/O SIGNALS TX[7:0] IRTX[7:0] RTS#[7:0] DTR#[7:0] EECK EECS 57 XR17V258 RESET STATE HIGH LOW HIGH HIGH LOW LOW EEDI LOW ...
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... XR17V258 66MHZ PCI BUS OCTAL UART WITH POWER MANAGEMENT SUPPORT ABSOLUTE MAXIMUM RATINGS Power Supply Range Voltage at Any Pin Operating Temperature Storage Temperature Package Dissipation Thermal Resistance (20x20x1.4mm 144-LQFP) ELECTRICAL CHARACTERISTICS DC ELECTRICAL CHARACTERISTICS FOR 3.3V SIGNALLING O O TA=-40 + INDUSTRIAL GRADE S P YMBOL ...
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... XR17V258 U N NITS OTES MHz On-chip osc. MHz Max 8Mbps using 0.3VCC out 0.7VCC out 0.6VCC out 0.18VCC out VCC+4 > Vin ≥ VCC < ...
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... XR17V258 66MHZ PCI BUS OCTAL UART WITH POWER MANAGEMENT SUPPORT F 19. PCI B C IGURE US ONFIGURATION CLK Host FRAME# Host AD[31:0] Host Target C/BE[3:0]# Host IRDY# Host TRDY# Target DEVSEL# Target CLK Host FRAME# Host AD[31:0] Host Target C/BE[3:0]# Host IRDY# Host TRDY# Target DEVSEL# Target ...
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... Note: PERR# and SERR are optional in a bus target application. Even Parity is on AD[31:0], C/BE[3:0]#, and PAR UART EGISTERS EAD PERATION FOR Data BYTE Byte Enable# = DWORD Data Parity Active Active 61 XR17V258 B DWORD YTE Data WORD Data Parity Active PCI_RD1 ...
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... XR17V258 66MHZ PCI BUS OCTAL UART WITH POWER MANAGEMENT SUPPORT F 21 IGURE EVICE ONFIGURATION REGISTERS TION CLK Host FRAME# Host Data AD[31:0] Address DWORD Host Target Bus C/BE[3:0]# Byte Enable# = DWORD CMD Host IRDY# Host TRDY# Target DEVSEL# Target Address PAR ...
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... Active Target Note: PERR# and SERR are optional in a bus target application. Even Parity is on AD[31:0], C/BE[3:0]#, and PAR R , UART R EGISTERS EGISTERS AND 8 13 Data Data Data Data Active Active 63 XR17V258 ECEIVE ATA URST EAD PERATION 18 23 Data Data Data Data ...
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... XR17V258 66MHZ PCI BUS OCTAL UART WITH POWER MANAGEMENT SUPPORT F 23. 3.3V PCI B C IGURE US LOCK 0.5VCC CLK 0.4VCC 0.3VCC T_val Output Delay T_on Tri-State Output Input (DC 66MH ) TO Z T_cyc T_low T_high Measurement Condition Parameters Vth = 0.6VCC Vtl = 0.2VCC V_trise Vtest = 0.4VCC Vtrise = 0 ...
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... Trigger Level Trigger Level BAUD RATE CLOCK of 16X NTERRUPT AT RIGGER EVEL DATA BITS (5- De-asserted at below trigger level 65 XR17V258 STOP BIT D6 D7 PARITY NEXT BIT DATA START BIT TXNOFIFO-1 STOP BIT D6 D7 First byte that PARITY BIT ...
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... XR17V258 66MHZ PCI BUS OCTAL UART WITH POWER MANAGEMENT SUPPORT PACKAGE DIMENSIONS 108 109 144 1 A Seating Plane Note: The control dimension is the millimeter column OTE SYMBOL α 144 LEAD LOW-PROFILE QUAD FLAT PACK ( 1.4 mm LQFP) ...
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... Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited. D ESCRIPTION Preliminary Datasheet Updated Timer/Counter Description to include ’Reset Timer’ command. Updated the 1.4mm-thick Quad Flat Pack package description from "TQFP" to "LQFP" consistent with JEDEC and Industry norms. Final Datasheet release. NOTICE uarttechsupport@exar.com 67 XR17V258 . ...
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... THE EVICE ................................................................................................................................ 2 ORDERING INFORMATION PIN DESCRIPTIONS ......................................................................................................... 3 FUNCTIONAL DESCRIPTION .......................................................................................... 8 PCI Local Bus Interface .............................................................................................................................................. 8 PCI Local Bus Configuration Space Registers ........................................................................................................... 8 Power Management Registers ................................................................................................................................... 8 EEPROM Interface ..................................................................................................................................................... 8 1.0 XR17V258 INTERNAL REGISTERS........................................................................................................ XR17V258 R IGURE HE EGISTER 1.1 PCI LOCAL BUS CONFIGURATION SPACE REGISTERS ............................................................................... PCI ...
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... RIORITY EVEL .......................................................................... 46 RIGGER ABLE AND EVEL ELECTION IRECTION ONTROL ELAY FROM RANSMIT EVELS HEN RIGGER ABLE IS ELECTED F ........................................................................................................................ 55 UNCTIONS 3.3V ................................................................. 58 FOR SIGNALLING II XR17V258 .......................................................... 31 16X S ................................................. 32 AMPLING EFR B -4. ....... 38 HADED BITS ARE ENABLED ................................................. 51 TO ECEIVE ................................................................ 53 ...
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... XR17V258 66MHZ PCI BUS OCTAL UART WITH POWER MANAGEMENT SUPPORT TA=-40o to +85oC (industrial grade) Supply Voltage, VCC = 3.0 - 3.6V.................................................................. 58 AC ELECTRICAL CHARACTERISTICS TA=-40o to+85oC (industrial grade) VCC = 3.0 - 3.6V............................................................................................. 59 F 19. PCI B C IGURE US ONFIGURATION F 20 IGURE EVICE ONFIGURATION AND F 21 IGURE EVICE ONFIGURATION REGISTERS F 22 ...