xr17v258 Exar Corporation, xr17v258 Datasheet - Page 52

• Manufacturer Part Number: xr17v258
• Description: 66mhz Pci Bus Octal Uart With Power Management Support
• Manufacturer: Exar Corporation

XR17V258
66MHZ PCI BUS OCTAL UART WITH POWER MANAGEMENT SUPPORT
MSR [3]: Transmitter Disable
This bit can be used to disable the transmitter by halting the Transmit Shift Register (TSR). When this bit is set
to a logic 1, the bytes already in the FIFO will not be sent out. Also, any more data loaded into the FIFO will
stay in the FIFO and will not be sent out. When this bit is set to a logic 0, the bytes currently in the TX FIFO will
be sent out. Please note that setting this bit to a logic 1 stops any character from going out. Also, this bit must
be a logic 0 for the Send Char Immediate function (see MCR[3]).
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MSR [2]: Receiver Disable
This bit can be used to disable the receiver by halting the Receive Shift Register (RSR). When this bit is set to
a logic 1, the receiver will operate in one of the following ways:
The receiver can be enabled and will start receiving characters by resetting this bit to a logic 0. The receiver
will operate in one of the following ways:
Any data that is in the RX FIFO can be read out at any time whether the receiver is disabled or not.
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MSR [1:0]: Reserved
This is a 8-bit general purpose register for the user to store temporary data. The content of this register is
preserved during sleep mode but becomes 0xFF (default) after a reset or a power off-on cycle.
This register controls the UART enhanced functions that are not available on ST16C554 or ST16C654.
FCTR[7:6]: TX and RX FIFO Trigger Table Select
These 2 bits select the transmit and receive FIFO trigger level table A, B, C or D. When table A, B, or C is
selected the auto RTS flow control trigger level is set to "next FIFO trigger level" for compatibility to ST16C550
and ST16C650 series. RTS/DTR# triggers on the next level of the RX FIFO trigger level, in another word, one
FIFO level above and one FIFO level below. See in
FCTR bits [7:6], i.e. if Table C is used on the receiver with RX FIFO trigger level set to 56 bytes, RTS/DTR#
output will de-assert at 60 and re-assert at 16.
FCTR[5]: Auto RS485 Enable
Auto RS485 half duplex control enable/disable.
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5.12
5.13
Logic 0 = Enable Transmitter (default).
Logic 1 = Disable Transmitter.
Logic 0 = Enable Receiver (default).
Logic 1 = Disable Receiver.
Logic 0 = Standard ST16C550 mode. Transmitter generates an interrupt when transmit holding register
(THR) becomes empty. Transmit Shift Register (TSR) may still be shifting data bit out.
Logic 1 = Enable Auto RS485 half duplex direction control. RTS# output changes from HIGH to LOW when
finished sending the last stop bit of the last character out of the TSR register. It changes from LOW to HIGH
when a data byte is loaded into the THR or transmit FIFO. The change to HIGH occurs prior sending the
start-bit. It also changes the transmitter interrupt from transmit holding to transmit shift register (TSR) empty.
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If a character is being received at the time of setting this bit, that character will be correctly received. No
more characters will be received.
If the receiver is idle at the time of setting this bit, one character will still be received fully. No more
characters will be received.
If the receiver is idle (RX pin is HIGH) at the time of setting this bit, the next character will be received
normally. It is recommended that the receiver be idle when resetting this bit to a logic 0.
If the receiver is not idle (RX pin is toggling) at the time of setting this bit, the RX FIFO will be filled with
unknown data.
SCRATCH PAD REGISTER (SPR) - Read/Write
FEATURE CONTROL REGISTER (FCTR) - Read/Write
52
Table 16
for complete selection with FCR bit [5:4] and
xr
REV. 1.0.0