xr17v258 Exar Corporation, xr17v258 Datasheet - Page 43

• Manufacturer Part Number: xr17v258
• Description: 66mhz Pci Bus Octal Uart With Power Management Support
• Manufacturer: Exar Corporation

xr
REV. 1.0.0
IER[4]: Reserved
IER[3]: Modem Status Interrupt Enable
The Modem Status Register interrupt is issued whenever any of the delta bits of the MSR register (bits [3:0]) is
set.
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IER[2]: Receive Line Status Interrupt Enable
An Overrun error, Framing error, Parity error or detection of a Break character will result in an LSR interrupt.
The V258 will issue an LSR interrupt immediately after receiving a character with an error. It will again re-issue
the interrupt (if the first one has been cleared by reading the LSR register) when the character with the error is
on the top of the FIFO, meaning the next one to be read out of the FIFO.
For example, let’s consider an incoming data stream of 0x55, 0xAA, etc. and that the character 0xAA has a
Parity error associated with it. Let’s assume that the character 0x55 has not been read out of the FIFO yet. The
V258v258 will issue an interrupt as soon as the stop bit of the character 0xAA is received. The LSR register will
have only the FIFO error bit (bit [7]) set and none of the other error bits (bits [4:1]) will be set, since the byte on
the top of the FIFO is 0x55 which does not have any errors associated with it. When this byte has been read
out, the V258 will issue another LSR interrupt and this time the LSR register will show the Parity bit (bit [2]) set.
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IER[1]: TX Ready Interrupt Enable
In non-FIFO mode, a TX interrupt is issued whenever the THR is empty. In the FIFO mode, an interrupt is
issued twice: once when the number of bytes in the TX FIFO falls below the programmed trigger level and
again when the TX FIFO becomes empty. When autoRS485 mode is enabled (FCTR bit [5] = 1), the second
interrupt is delayed until the transmitter (both the TX FIFO and the TX Shift Register) is empty.
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IER[0]: RX Interrupt Enable
The receive data ready interrupt will be issued when RHR has a data character in the non-FIFO mode or when
the receive FIFO has reached the programmed trigger level in the FIFO mode.
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The UART provides multiple levels of prioritized interrupts to minimize external software interaction. The
Interrupt Status Register (ISR) provides the user with six interrupt status bits. Performing a read cycle on the
ISR will give the user the current highest pending interrupt level to be serviced, others queue up for next
service. No other interrupts are acknowledged until the pending interrupt is serviced. The Interrupt Source
Table,
associated with each of these interrupt levels.
5.5
Logic 0 = Disable the modem status register interrupt (default).
Logic 1 = Enable the modem status register interrupt.
Logic 0 = Disable the receiver line status interrupt (default).
Logic 1 = Enable the receiver line status interrupt.
Logic 0= Disable Transmit Ready Interrupt (default).
Logic 1 = Enable Transmit Ready Interrupt.
Logic 0 = Disable the receive data ready interrupt (default).
Logic 1 = Enable the receiver data ready interrupt.
Table 15
Interrupt Status Register (ISR) - Read Only
, shows the data values (bit [5:0]) for the six prioritized interrupt levels and the interrupt sources
66MHZ PCI BUS OCTAL UART WITH POWER MANAGEMENT SUPPORT
43
XR17V258