xr17v258 Exar Corporation, xr17v258 Datasheet - Page 41

• Manufacturer Part Number: xr17v258
• Description: 66mhz Pci Bus Octal Uart With Power Management Support
• Manufacturer: Exar Corporation

xr
REV. 1.0.0
The receiver section contains an 8-bit Receive Shift Register (RSR) and Receive Holding Register (RHR). The
RSR uses the 16X or 8X clock for timing. It verifies and validates every bit on the incoming character in the
middle of each data bit. On the falling edge of a start or false start bit, an internal receiver counter starts
counting at the 16X or 8X clock rate. After 8 or 4 clocks the start bit period should be at the center of the start
bit. At this time the start bit is sampled and if it is still a logic 0 it is validated. Evaluating the start bit in this
manner prevents the receiver from assembling a false character. The rest of the data bits and stop bits are
sampled and validated in this same manner to prevent false framing. If there were any error(s), they are
reported in the LSR register bits [4:1]. Upon unloading the receive data byte from RHR, the receive FIFO
pointer is bumped and the error flags are immediately updated to reflect the status of the data byte in RHR
register. RHR can generate a receive data ready interrupt upon receiving a character or delay until it reaches
the FIFO trigger level. Furthermore, data delivery to the host is guaranteed by a receive data ready time-out
function when receive data does not reach the receive FIFO trigger level. This time-out delay is 4 word lengths
as defined by LCR bits [1:0] plus 12 bits time. The RHR interrupt is enabled by IER bit [0].
F
4.7
4.7.1
4.7.2
IGURE
Receive Data
Byte and Errors
16X or 8X Sampling
Clock (8XMODE Reg.)
F
IGURE
18. R
Receiver
64 bytes by 11-
bit wide FIFO
Receiver Operation with FIFO
Receiver Operation in non-FIFO Mode
17. R
ECEIVER
(8XMODE Register)
and Errors
ECEIVER
Data Byte
16X or 8X Clock
Receive
O
PERATION IN
O
Receive Data Shift
Register (RSR)
PERATION IN NON
66MHZ PCI BUS OCTAL UART WITH POWER MANAGEMENT SUPPORT
Receive Data
LSR bits
Receive
Flags in
(64-byte)
Error
FIFO
FIFO
Data
4:2
Receive Data Shift
Register (RSR)
AND
Holding Register
Receive Data
-FIFO M
F
Data falls to 40
FIFO Trigger=48
Data fills to 56
Validation
(RHR)
LOW
Data Bit
Example:
- FIFO trigger level set at 48 bytes
- RTS/DTR hyasteresis set at +/-8 chars.
C
41
ONTROL
ODE
Validation
Data Bit
RTS#/DTR# re-asserts when data falls below
the trigger level to restart remote transmitter.
Enable by EFR bit-6=1, MCR bit-2.
RTS#/DTR# de-asserts when data fills above
the trigger level to suspend remote transmitter.
Enable by EFR bit-6=1, MCR bit-2.
RHR Interrupt (ISR bit-2) is programmed
at FIFO trigger level (RXTRG).
FIFO is Enable by FCR bit-0=1
M
ODE
RHR Interrupt (ISR bit-2)
Receive Data Characters
Receive Data Characters
RXFIFO1
XR17V258
RXFIFO1