xr17v258 Exar Corporation, xr17v258 Datasheet - Page 38
xr17v258
Manufacturer Part Number
xr17v258
Description
66mhz Pci Bus Octal Uart With Power Management Support
Manufacturer
Exar Corporation
Datasheet
1.XR17V258.pdf
(70 pages)
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A
XR17V258
66MHZ PCI BUS OCTAL UART WITH POWER MANAGEMENT SUPPORT
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 1
0 0 1 0
0 0 0 1
0 0 1 0
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
1 0 0 0
A3-A0
T
DDRESS
ABLE
14: UART CHANNEL CONFIGURATION REGISTERS DESCRIPTION.
FCTR
N
MCR
RHR
DLM
MSR
MSR
THR
DLD
FCR
LCR
SPR
R
LSR
DLL
IER
ISR
AME
EG
R
W
R/W
R/W
R/W
R/W
R/W
R/W
R/W RX FIFO
R/W
R/W
EAD
W
W
W
RITE
R
R
R
/
RX FIFO
Enable
Enable
Trigger
Enable
Divisor
E
RS485
B
BIT [7]
BIT [7]
BIT [7]
BIT [7]
FIFOs
DSR#
DLY-3
Bit [7]
Pres-
Table
CTS/
BRG
caler
Bit [1]
TRG
RROR
IT
Int.
CD
0/
0/
0
[7]
RX FIFO
Enable
Enable
Trigger
Enable
Set TX
RS485
B
BIT [6]
BIT [6]
BIT [6]
BIT [6]
Empty
FIFOs
DTR#
Break
DLY-2
Bit [6]
Bit [0]
Table
RTS/
TRG
TSR
IT
Int.
IR
RI
0/
0/
0
[6]
Char. Int.
TX FIFO
Set Par-
Xoff/Sp.
XonAny
Enable
Trigger
Enable
B
RS485
RS485
Empty
DLY-1
Bit [5]
Bit [5]
Bit [5]
Bit [5]
Delta-
Bit [5]
Xon/
Flow
THR
DSR
Auto
Cntl
IT
ity
0/
0/
0/
0/
0
[5]
Even Par-
Loopback
RX Break
Xoff/spe-
RX Input
TX FIFO
Invert IR
cial char
38
Internal
Trigger
Enable
RS485
B
Bit [4]
Bit [4]
Bit [4]
Bit [4]
DLY-0
Bit [4]
CTS
IT
ity
0/
0/
0
0
[4]
Framing
TX char
Immedi-
Modem
Disable
Enable
Source
Enable
(OP2)
B
Status
Bit [3]
Bit [3]
Bit [3]
Bit [3]
Bit [3]
Bit [3]
Parity
Bit [3]
Bit [3]
Mode
Delta
DMA
Error
RTS/
DTR
CD#
Hyst
INT
IT
Int.
ate
RX
TX
[3]
1
Stop Bits
TX FIFO
Flow Sel
RX Line
RX Par-
ity Error
Disable
Enable
Source
(OP1)
B
Status
Bit [2]
Bit [2]
Bit [2]
Bit [2]
Bit [2]
Bit [2]
Reset
Bit [2]
Bit [2]
Delta
RTS/
RTS/
DTR
DTR
Hyst
INT
IT
RI#
Int.
RX
[2]
1
S
HADED BITS ARE ENABLED BY
RX FIFO
Pin Con-
Overrun
Enable
Source
Length
Empty
B
DSR#
Bit [1]
Bit [1]
Bit [1]
Bit [1]
Bit [1]
Bit [1]
Reset
Bit [1]
RTS#
Bit [1]
Bit [1]
Word
Delta
RTS/
DTR
Hyst
INT
Int.
trol
RX
IT
TX
[1]
Pin Con-
RX Data
RX Data
Enable
Source
Enable
Length
B
xr
FIFOs
Ready
Bit [0]
Bit [0]
Bit [0]
Bit [0]
Bit [0]
Bit [0]
Bit [0]
DTR#
CTS#
Bit [0]
Bit [0]
Word
Delta
RTS/
DTR
Hyst
INT
IT
Int.
trol
[0]
REV. 1.0.0
User Data
EFR B
LCR[7]=0
LCR[7]=0
LCR[7]=1
LCR[7]=1
LCR[7]=1
LCR[7]=0
LCR[7]=0
LCR[7]=0
C
OMMENT
IT
-4.