XR17V258IV-F Exar Corporation, XR17V258IV-F Datasheet - Page 56
![IC UART PCI BUS OCTAL 144LQFP](/photos/29/6/290685/xr17v358_sml.jpg)
XR17V258IV-F
Manufacturer Part Number
XR17V258IV-F
Description
IC UART PCI BUS OCTAL 144LQFP
Manufacturer
Exar Corporation
Type
Octal UARTr
Datasheet
1.XR17V258IVTR-F.pdf
(69 pages)
Specifications of XR17V258IV-F
Number Of Channels
8
Package / Case
144-LQFP
Features
*
Fifo's
64 Byte
Protocol
RS485
Voltage - Supply
3.3V, 5V
With Auto Flow Control
Yes
With Irda Encoder/decoder
Yes
With False Start Bit Detection
Yes
With Modem Control
Yes
Mounting Type
Surface Mount
Data Rate
8 Mbps
Supply Voltage (max)
3.6 V
Supply Voltage (min)
3 V
Supply Current
4 mA
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 45 C
Mounting Style
SMD/SMT
Operating Supply Voltage
3 V to 3.6 V
No. Of Channels
8
Uart Features
Tx/Rx FIFO Counters
Supply Voltage Range
3V To 3.6V
Operating Temperature Range
-40°C To +85°C
Digital Ic Case Style
LQFP
No. Of Pins
144
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XR17V258IV-F
Manufacturer:
EXAR
Quantity:
295
Company:
Part Number:
XR17V258IV-F
Manufacturer:
Exar Corporation
Quantity:
10 000
Part Number:
XR17V258IV-F
Manufacturer:
EXAR/艾科嘉
Quantity:
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XR17V258
66MHZ PCI BUS OCTAL UART WITH POWER MANAGEMENT SUPPORT
EFR[6]: Auto RTS or DTR Flow Control Enable
RTS#/DTR# output may be used for hardware flow control by setting EFR bit [6] to logic 1. When Auto RTS/
DTR is selected, an interrupt will be generated when the receive FIFO is filled to the programmed trigger level
and RTS/DTR# will de-assert (HIGH) at the next upper trigger or selected hysteresis level. RTS/DTR# will re-
assert (LOW) when FIFO data falls below the next lower trigger or selected hysteresis level (see FCTR bits 4-
7). The RTS# or DTR# output must be asserted (LOW) before the auto RTS/DTR can take effect. The selection
for RTS# or DTR# is through MCR bit [2]. RTS/DTR# pin will function as a general purpose output when
hardware flow control is disabled.
•
•
EFR[5]: Special Character Detect Enable
•
•
EFR[4]: Enhanced Function Bits Enable
Enhanced function control bit. This bit enables the enhanced functions in IER bits [7:5], ISR bits [5:4], FCR
bits [5:4], MCR bits [7:5,3:2] and MSR [7:2] bits to be modified. After modifying any enhanced bits, EFR bit [4]
can be set to a logic 0 to latch the new values. This feature prevents legacy software from altering or
overwriting the enhanced functions once set. Normally, it is recommended to leave it enabled.
•
•
EFR[3:0]: Software Flow Control Select
Combinations of software flow control can be selected by programming these bits, as shown in
below.
Logic 0 = Automatic RTS/DTR flow control is disabled (default).
Logic 1 = Enable Automatic RTS/DTR flow control.
Logic 0 = Special Character Detect Disabled (default).
Logic 1 = Special Character Detect Enabled. The UART compares each incoming receive character with
data in Xoff-2 register. If a match exists, the received data will be transferred to FIFO and ISR bit [4] will be
set to indicate detection of the special character. bit [0] corresponds with the LSB bit for the receive
character. If flow control is set for comparing Xon1, Xoff1 (EFR [1:0]=10) then flow control and special
character work normally. However, if flow control is set for comparing Xon2, Xoff2 (EFR[1:0]=01) then flow
control works normally, but Xoff2 will not go to the FIFO, and will generate an Xoff interrupt and a special
character interrupt.
Logic 0 = Disable write access to the enhanced function bits: IER bits [7:5], ISR bits [5:4], FCR bits [5:4],
MCR bits [7:5, 3:2] and MSR [7:2] bits. After a reset, all these bits are set to a logic 0 to be compatible with
ST16C550 mode (default).
Logic 1 = Enables write access to the enhanced function bits: IER bits [7:5], ISR bits [5:4], FCR bits [5:4],
MCR bits [7:5, 3:2] and MSR [7:2] bits.
56
REV. 1.0.2
Table 21