XR17V258IV-F Exar Corporation, XR17V258IV-F Datasheet - Page 49
![IC UART PCI BUS OCTAL 144LQFP](/photos/29/6/290685/xr17v358_sml.jpg)
XR17V258IV-F
Manufacturer Part Number
XR17V258IV-F
Description
IC UART PCI BUS OCTAL 144LQFP
Manufacturer
Exar Corporation
Type
Octal UARTr
Datasheet
1.XR17V258IVTR-F.pdf
(69 pages)
Specifications of XR17V258IV-F
Number Of Channels
8
Package / Case
144-LQFP
Features
*
Fifo's
64 Byte
Protocol
RS485
Voltage - Supply
3.3V, 5V
With Auto Flow Control
Yes
With Irda Encoder/decoder
Yes
With False Start Bit Detection
Yes
With Modem Control
Yes
Mounting Type
Surface Mount
Data Rate
8 Mbps
Supply Voltage (max)
3.6 V
Supply Voltage (min)
3 V
Supply Current
4 mA
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 45 C
Mounting Style
SMD/SMT
Operating Supply Voltage
3 V to 3.6 V
No. Of Channels
8
Uart Features
Tx/Rx FIFO Counters
Supply Voltage Range
3V To 3.6V
Operating Temperature Range
-40°C To +85°C
Digital Ic Case Style
LQFP
No. Of Pins
144
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XR17V258IV-F
Manufacturer:
EXAR
Quantity:
295
Company:
Part Number:
XR17V258IV-F
Manufacturer:
Exar Corporation
Quantity:
10 000
Part Number:
XR17V258IV-F
Manufacturer:
EXAR/艾科嘉
Quantity:
20 000
REV. 1.0.2
LCR[5]: TX and RX Parity Select
If the parity bit is enabled, LCR bit [5] selects the forced parity format.
•
•
•
LCR[4]: TX and RX Parity Select
If the parity bit is enabled with LCR bit [3] set to a logic 1, LCR bit [4] selects the even or odd parity format.
•
•
LCR[3]: TX and RX Parity Select
Parity or no parity can be selected via this bit. The parity bit is a simple way used in communications for data
integrity check. See
•
•
LCR[2]: TX and RX Stop-bit Length Select
The length of stop bit is specified by this bit in conjunction with the programmed word length.
LCR[1:0]: TX and RX Word Length Select
These two bits specify the word length to be transmitted or received.
LCR bit [5] = logic 0, parity is not forced (default).
LCR bit [5] = logic 1 and LCR bit [4] = logic 0, parity bit is forced to a logical 1for the transmit and receive
data.
LCR bit [5] = logic 1 and LCR bit [4] = logic 1, parity bit is forced to a logical 0 for the transmit and receive
data.
Logic 0 = ODD Parity is generated by forcing an odd number of logic 1’s in the transmitted character. The
receiver must be programmed to check the same format (default).
Logic 1 = EVEN Parity is generated by forcing an even the number of logic 1’s in the transmitted character.
The receiver must be programmed to check the same format.
Logic 0 = No parity.
Logic 1 = A parity bit is generated during the transmission while the receiver checks for parity error of the
data character received.
LCR
Table 18
BIT [5]
X
0
0
1
1
above for parity selection summary.
BIT [1]
BIT [2]
66MHZ PCI BUS OCTAL UART WITH POWER MANAGEMENT SUPPORT
LCR
0
0
1
1
0
1
1
BIT [4]
T
X
0
1
0
1
ABLE
BIT [0]
LENGTH
5,6,7,8
18: P
W
6,7,8
0
1
0
1
ORD
5
LCR
ARITY
BIT [3]
49
0
1
1
1
1
P
ROGRAMMING
S
W
TOP BIT LENGTH
(B
ORD LENGTH
5 (default)
1 (default)
IT TIME
Forced parity to space, “0”
1-1/2
Force parity to mark, “1”
6
7
8
2
P
(
ARITY SELECTION
S
))
Even parity
Odd parity
No parity
XR17V258