M052LAN Nuvoton Technology Corporation of America, M052LAN Datasheet - Page 257

• Manufacturer Part Number: M052LAN
• Description: IC MCU 32BIT 8KB FLASH 48LQFP
• Manufacturer: Nuvoton Technology Corporation of America
• Series: NuMicro M051™r

Specifications of M052LAN

• Core Processor: ARM Cortex-M0
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 40
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 8x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

6.8.4
6.8.4.1 One –Shot mode
6.8.4.2 Periodic mode
6.8.4.3 Toggle mode
NuMicro M051
Timer controller provides one-shot, period and toggle modes operation. Each operating function
mode is shown as following:
If timer is operated at one-shot mode and CEN (timer enable bit) is set to 1, the timer counter
starts up counting. Once the timer counter value reaches timer compare register (TCMPR) value,
if IE (interrupt enable bit) is set to 1’b1, then the timer interrupt flag is set and the interrupt signal
is generated and sent to NVIC to inform CPU. It indicates that the timer counting overflow
happens. If IE (interrupt enable bit) is set to 0, no interrupt signal is generated. In this operating
mode, once the timer counter value reaches timer compare register (TCMPR) value, the timer
counter value goes back to counting initial value and CEN (timer enable bit) is cleared to 0 by
timer controller. Timer counting operation stops, once the timer counter value reaches timer
compare register (TCMPR) value. That is to say, timer operates timer counting and compares
with TCMPR value function only one time after programming the timer compare register (TCMPR)
value and CEN (timer enable bit) is set to 1. So, this operating mode is called One-Shot mode.
If timer is operated at period mode and CEN (timer enable bit) is set to 1, the timer counter starts
up counting. Once the timer counter value reaches timer compare register (TCMPR) value, if IE
(interrupt enable bit) is set to 1’b1, then the timer interrupt flag is set and the interrupt signal is
generated and sent to NVIC to inform CPU. It indicates that the timer counting overflow happens.
If IE (interrupt enable bit) is set to 0, no interrupt signal is generated. In this operating mode, once
the timer counter value reaches timer compare register (TCMPR) value, the timer counter value
goes back to counting initial value and CEN is kept at 1 (counting enable continuously). The timer
counter operates up counting again. If the interrupt flag is cleared by software, once the timer
counter value reaches timer compare register (TCMPR) value and IE (interrupt enable bit) is set
to 1’b1, then the timer interrupt flag is set and the interrupt signal is generated and sent to NVIC
to inform CPU again. That is to say, timer operates timer counting and compares with TCMPR
value function periodically. The timer counting operation doesn’t stop until the CEN is set to 0.
The interrupt signal is also generated periodically. So, this operating mode is called Periodic
mode.
If timer is operated at toggle mode and CEN (timer enable bit) is set to 1, the timer counter starts
up counting. Once the timer counter value reaches timer compare register (TCMPR) value, if IE
(interrupt enable bit) is set to 1’b1, then the timer interrupt flag is set and the interrupt signal is
generated and sent to NVIC to inform CPU. It indicates that the timer counting overflow happens.
The associated toggle output (tout) signal is set to 1. In this operating mode, once the timer
counter value reaches timer compare register (TCMPR) value, the timer counter value goes back
to counting initial value and CEN is kept at 1 (counting enable continuously). The timer counter
operates up counting again. If the interrupt flag is cleared by software, once the timer counter
value reaches timer compare register (TCMPR) value and IE (interrupt enable bit) is set to 1, then
the timer interrupt flag is set and the interrupt signal is generated and sent to NVIC to inform CPU
Timer Operation Mode
™
Series Technical Reference Manual
- 257 -
Publication Release Date: Sept 14, 2010
Revision V1.2