M052LAN Nuvoton Technology Corporation of America, M052LAN Datasheet - Page 298

• Manufacturer Part Number: M052LAN
• Description: IC MCU 32BIT 8KB FLASH 48LQFP
• Manufacturer: Nuvoton Technology Corporation of America
• Series: NuMicro M051™r

Specifications of M052LAN

• Core Processor: ARM Cortex-M0
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 40
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 8x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Interrupt Status Control Register (UA_ISR)
[15]
[14]
[13:8]
[7]
[6]
[4]
[3]
[2:0]
[5]
NuMicro M051
RX_OVER
RX_EMPTY
RX_POINTER
Reserved
BIF
FEF
PEF
RS-
485_ADD_DETF
Reserved
UA_THR, TX_POINTER increases one. When one byte of TX FIFO is transferred to
Transmitter Shift Register, TX_POINTER decreases one.
Receiver FIFO Over (Read Only)
This bit indicates RX FIFO overrunning or not.
If the number of bytes of received data is greater than RX_FIFO (UA_RBR) size, 15
bytes of UART0/UART1, this bit will be set. Otherwise is cleared by hardware.
Receiver FIFO Empty (Read Only)
This bit initiate RX FIFO empty or not.
When the last byte of RX FIFO has been read by CPU, hardware sets this bit high. It
will be cleared when UART receives any new data.
RX FIFO Pointer (Read Only)
This field indicates the RX FIFO Buffer Pointer. When UART receives one byte from
external device, RX_POINTER increases one. When one byte of RX FIFO is read by
CPU, RX_POINTER decreases one.
Reserved
Break Interrupt Flag (Read Only)
This bit is set to a logic 1 whenever the received data input(RX) is held in the
“spacing state” (logic 0) for longer than a full word transmission time (that is, the total
time of “start bit” + data bits + parity + stop bits) and is reset whenever the CPU
writes 1 to this bit.
NOTE: This bit is read only, but can be cleared by writing ‘1’ to it.
Framing Error Flag (Read Only)
This bit is set to logic 1 whenever the received character does not have a valid “stop
bit” (that is, the stop bit following the last data bit or parity bit is detected as a logic 0),
and is reset whenever the CPU writes 1 to this bit.
NOTE: This bit is read only, but can be cleared by writing ‘1’ to it.
Parity Error Flag (Read Only)
This bit is set to logic 1 whenever the received character does not have a valid “parity
bit”, and is reset whenever the CPU writes 1 to this bit.
NOTE: This bit is read only, but can be cleared by writing ‘1’ to it.
RS-485 Address Byte Detection Flag (Read Only)
This bit is set to logic 1 and set UA_ALT_CSR [RS-485_ADD_EN] whenever in RS-
485 mode the receiver detect any address byte received address byte character (bit9
= ‘1’) bit, and it is reset whenever the CPU writes 1 to this bit.
Note: This field is used for RS-485 function mode.
NOTE: This bit is read only, but can be cleared by writing ‘1’ to it.
Reserved
™
Series Technical Reference Manual
- 298 -
Publication Release Date: Sep 14, 2010
Revision V1.2