AT89LP52-20JU Atmel, AT89LP52-20JU Datasheet - Page 26

• Manufacturer Part Number: AT89LP52-20JU
• Description: IC MCU 8051 8K FLASH SPI 44PLCC
• Manufacturer: Atmel
• Series: 89LPr

Specifications of AT89LP52-20JU

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 36
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-LCC (J-Lead)
• Processor Series: AT89x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: Serial
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 36
• Number Of Timers: 3
• Operating Supply Voltage: 2.7 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

5.3.1
26
AT89LP51/52 - Preliminary
Data Pointer Update
Table 5-1.
The Dual Data Pointers on the AT89LP51/52 include two features that control how the data
pointers are updated. The data pointer decrement bits, DPD1 and DPD0 in AUXR1, configure
the INC DPTR instruction to act as DEC DPTR. The resulting operation will depend on DPS as
shown in
MOVX.
Instruction
JMP @A+DPTR
MOV DPTR, #data16
MOV /DPTR, #data16
INC DPTR
INC /DPTR
MOVC A,@A+DPTR
MOVC A,@A+/DPTR
MOVX A,@DPTR
MOVX A,@/DPTR
MOVX @DPTR, A
MOVX @/DPTR, A
• Bit 2 of AUXR1 is hard-wired as a logic 0. The DPS bit may be toggled (to switch data
• In some cases, both data pointers must be used simultaneously. To prevent frequent toggling
pointers) simply by incrementing the AUXR1 register, without altering other bits in the register
unintentionally. This is the preferred method when only a single data pointer will be used at
one time.
of DPS, the AT89LP51/52 supports a prefix notation for selecting the opposite data pointer
per instruction. All DPTR instructions, with the exception of JMP @A+DPTR, when prefixed
with an 0A5H opcode will use the inverse value of DPS (DPS) to select the data pointer.
Some assemblers may support this operation by using the /DPTR operand. For example, the
following code performs a block copy within EDATA:
EX:
COPY: MOVX A, @DPTR
For assemblers that do not support this notation, the 0A5H prefix must be declared in-line:
EX:
A summary of data pointer instructions with fast context switching is listed
Table
INC
MOV
MOV
MOV
MOV
INC
MOVX @/DPTR, A
INC
DJNZ R7, COPY
DB
INC
Data Pointer Instructions
5-2. These bits also control the direction of auto-updates during MOVC and
AUXR1 ; Toggle DPS
AUXR1, #00H
DPTR, #SRC
/DPTR, #DST
R7, #BLKSIZE
DPTR
/DPTR
0A5H
DPTR
; DPS = 0
; load source address to dptr0
; load destination address to dptr1
; number of bytes to copy
; read source (dptr0)
; next src (dptr0+1)
; write destination (dptr1)
; next dst (dptr1+1)
; equivalent to INC /DPTR
DPS = 0
JMP @A+DPTR0
MOV DPTR0, #data16
MOV DPTR1, #data16
INC DPTR0
INC DPTR1
MOVC A,@A+DPTR0
MOVC A,@A+DPTR1
MOVX A,@DPTR0
MOVX A,@DPTR1
MOVX @DPTR0, A
MOVX @DPTR1, A
Operation
DPS = 1
JMP @A+DPTR1
MOV DPTR1, #data16
MOV DPTR0, #data16
INC DPTR1
INC DPTR0
MOVC A,@A+DPTR1
MOVC A,@A+DPTR0
MOVX A,@DPTR1
MOVX A,@DPTR0
MOVX @DPTR1, A
MOVX @DPTR0, A
inTable
3709B–MICRO–12/10
5-1.