AT89LP52-20JU Atmel, AT89LP52-20JU Datasheet - Page 40

• Manufacturer Part Number: AT89LP52-20JU
• Description: IC MCU 8051 8K FLASH SPI 44PLCC
• Manufacturer: Atmel
• Series: 89LPr

Specifications of AT89LP52-20JU

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 36
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-LCC (J-Lead)
• Processor Series: AT89x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: Serial
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 36
• Number Of Timers: 3
• Operating Supply Voltage: 2.7 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

10. I/O Ports
10.1
40
Port Configuration
AT89LP51/52 - Preliminary
The AT89LP51/52 can be configured for between 32 and 36 I/O pins. The exact number of I/O
pins available depends on the clock, external memory and package type as shown in
1.
Table 10-1.
Each 8-bit port on the AT89LP51/52 may be configured in one of four modes: quasi-bidirectional
(standard 8051 port outputs), push-pull output, open-drain output, or input-only. Port modes may
be assigned in software on a port-by-port basis as shown in
listed in
When the fuse is enabled, all port pins default to input-only mode after reset. When the fuse is
disabled, all port pins on P1, P2 and P3 default to quasi-bidirectional mode after reset and are
weakly pulled high. P0 is set to Open-drain mode. P4 always operates in quasi-bidirectional
mode.
Each port pin also has a Schmitt-triggered input for improved input noise rejection. During
Power-down all the Schmitt-triggered inputs are disabled with the exception of P3.2 (INT0), P3.3
(INT1), RST, P4.6 (XTAL1) and P4.7 (XTAL2). Therefore, P3.2, P3.3, P4.6 and P4.7 should not
be left floating during Power-down.
.
Table 10-2.
Clock Source
External Crystal or
Resonator
External Clock
Internal RC
Oscillator
PxM0
0
0
1
1
Table
I/O Pin Configurations
Configuration Modes for Port x
10-3. The Tristate-Port User Fuse determines the default state of the port pins.
External Program Access
PxM1
Yes (PSEN+ALE+P0+P2)
Yes (PSEN+ALE+P0+P2)
Yes (PSEN+ALE+P0+P2)
0
1
0
1
No
No
No
Port Mode
Quasi-bidirectional
Push-pull Output
Input Only (High Impedance)
Open-Drain Output
Yes (ALE+RD+WR+P0)
Yes (ALE+RD+WR+P0)
Yes (ALE+RD+WR+P0)
External Data Access
Yes (RD+WR)
Yes (RD+WR)
Yes (RD+WR)
Table 10-2
No
No
No
No
No
No
using the PMOD register
Number of I/O
3709B–MICRO–12/10
Pins
14
16
31
34
15
17
32
35
16
18
33
36
Table 10-