ATMEGA32M1-AUR Atmel, ATMEGA32M1-AUR Datasheet - Page 207
ATMEGA32M1-AUR
Manufacturer Part Number
ATMEGA32M1-AUR
Description
IC MPU AVR 32K 20MHZ 32TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA32M1-AUR
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
CAN, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Program Memory Size
32KB (16K x 16)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 11x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
32-TQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of I /o
-
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20.5.5
20.5.5.1
Figure 20-7. Busy Signal in LIN Mode
8209D–AVR–11/10
1) LBUSY
2) LBUSY
3) LBUSY
LIN bus
Busy Signal
Busy Signal in LIN Mode
LCMD=Tx Header
BREAK
Node providing the master task
Field
Table 20-3.
The LIN configuration is independent of the programmed LIN protocol.
The listening mode connects the internal Tx LIN and the internal Rx LIN together. In this mode,
the TXLIN output pin is disabled and the RXLIN input pin is always enabled. The same scheme
is available in UART mode.
Figure 20-6. Listening Mode
LBUSY bit flag in LINSIR register is the image of the BUSY signal. It is set and cleared by hard-
ware. It signals that the controller is busy with LIN or UART communication.
Mode
UART
HEADER
SYNC
LCONF[1..0]
LISTEN
Configuration Table versus Mode
Rx LIN
00
01
10
11
Tx LIN
internal
internal
Node providing neither the master task, neither a slave task
Field
b
b
b
b
PROTECTED
IDENTIFIER
LIDOK
Field
FRAME SLOT
1
0
Listening mode, 8-bit data, no parity & 1 stop-bit
LCMD=Tx or Rx Response
DATA-0
8-bit data, even parity & 1 stop-bit
8-bit data, odd parity & 1 stop-bit
8-bit data, no parity & 1 stop-bit
ATmega16M1/32M1/64M1
Field
Configuration
Node providing a slave task
RESPONSE
DATA-n
RXLIN
TXLIN
Field
LTXOK or LRXOK
CHECKSUM
Field
207
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