LPC1224FBD64/201 NXP Semiconductors, LPC1224FBD64/201 Datasheet - Page 41

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LPC1224FBD64/201

Manufacturer Part Number
LPC1224FBD64/201
Description
MCU 32BIT 32K FLASH 4K 64-LQFP
Manufacturer
NXP Semiconductors
Datasheet

Specifications of LPC1224FBD64/201

Core Processor
ARM Cortex-M0
Core Size
32-Bit
Speed
45MHz
Connectivity
I²C, IrDA, Microwire, SPI, SSI, SSP, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, POR, WDT
Number Of I /o
55
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
568-5155
LPC1224FBD64/201
NXP Semiconductors
LPC122X
Objective data sheet
10.4 ADC characteristics
Table 9.
T
3.6 V.
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[8]
Symbol
E
V
C
E
E
E
E
f
c(ADC)
amb
IA
D
L(adj)
O
G
T
ia
Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply
voltages.
Conditions: V
The ADC is monotonic, there are no missing codes.
The differential linearity error (E
See
The integral non-linearity (E
the ideal transfer curve after appropriate adjustment of gain and offset errors. See
The offset error (E
straight line which fits the ideal curve. See
The gain error (E
curve after removing offset error, and the straight line which fits the ideal transfer curve. See
The absolute error (E
curve of the non-calibrated ADC and the ideal transfer curve. See
=
40
Figure
ADC static characteristics
C to +85
Parameter
analog input voltage
analog input capacitance
differential linearity error
integral non-linearity
offset error
gain error
absolute error
ADC conversion frequency
17.
SS
All information provided in this document is subject to legal disclaimers.
= 0 V, V
G
O
) is the relative difference in percent between the straight line fitting the actual transfer
) is the absolute difference between the straight line which fits the actual curve and the
C unless otherwise specified; ADC frequency 9 MHz, V
T
) is the maximum difference between the center of the steps of the actual transfer
Rev. 1.2 — 29 March 2011
DD(3V3)
L(adj)
= 3.3 V.
D
) is the peak difference between the center of the steps of the actual and
) is the difference between the actual step width and the ideal step width.
Conditions
Figure
17.
32-bit ARM Cortex-M0 microcontroller
[2][3][4]
[2][5]
[2][6]
[2][7]
[2][8]
Figure
Min
0
-
-
-
-
-
-
-
17.
Typ
-
-
-
-
-
-
-
-
[1]
Figure
DD(3V3)
LPC122x
© NXP B.V. 2011. All rights reserved.
Max
V
1
 1
 2.5
 1
 3
 3
257
DD(3V3)
17.
= 3.0 V to
Figure
Unit
V
pF
LSB
LSB
LSB
LSB
LSB
kHz
41 of 60
17.

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