ATMEGA649P-AUR Atmel, ATMEGA649P-AUR Datasheet - Page 21
ATMEGA649P-AUR
Manufacturer Part Number
ATMEGA649P-AUR
Description
IC MCU AVR 64KB FLASH 64TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA649P-AUR
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
SPI, UART/USART, USI
Peripherals
Brown-out Detect/Reset, LCD, POR, PWM, WDT
Number Of I /o
54
Program Memory Size
64KB (32K x 16)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Manufacturer
Quantity
Price
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7.2
7.2.1
8284A–AVR–10/10
SRAM Data Memory
Data Memory Access Times
Figure 7-2
The ATmega169A/169PA/329A/329PA/649A/649P/3290A/3290PA/6490A/6490P is a complex
microcontroller with more peripheral units than can be supported within the 64 locations
reserved in the Opcode for the IN and OUT instructions. For the Extended I/O space from 0x60 -
0xFF in SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used.
T h e
(ATmega329A/329PA/3290A/3290PA/649A/649P/6490A/6490P) data memory locations
address both the Register File, the I/O memory, Extended I/O memory, and the internal data
SRAM. The first 32 locations address the Register File, the next 64 location the standard I/O
memory, then 160 locations of Extended I/O memory, and the next 1024/2048/4096 locations
address the internal data SRAM.
The five different addressing modes for the data memory cover: Direct, Indirect with Displace-
ment, Indirect, Indirect with Pre-decrement, and Indirect with Post-increment. In the Register
File, registers R26 to R31 feature the indirect addressing pointer registers.
The direct addressing reaches the entire data space.
The Indirect with Displacement mode reaches 63 address locations from the base address given
by the Y- or Z-register.
When using register indirect addressing modes with automatic pre-decrement and post-incre-
ment, the address registers X, Y, and Z are decremented or incremented.
The 32 general purpose working registers, 64 I/O Registers, 160 Extended I/O Registers, and
t h e
ATmega169A/169PA/329A/329PA/3290A/3290PA/649A/649P/6490A/6490P are all accessible
through all these addressing modes. The Register File is described in
ter File” on page
Figure 7-2.
This section describes the general access timing concepts for internal memory access. The
internal data SRAM access is performed in two clk
ATmega169A/169PA/329A/329PA/649A/649P/3290A/3290PA/6490A/6490P
1 , 0 2 4 / 2 , 0 4 8
shows how the SRAM Memory is organized.
l o w e r
Data Memory Map
15.
1 2 8 0
X 8
160 Ext I/O Reg.
64 I/O Registers
Data Memory
Internal SRAM
b y t e s
32 Registers
(1024 X 8)
(2048 x 8)
(4096 x 8)
( A T m e g a 1 6 9 A / 1 6 9 P A )
o f
0x04FF/0x08FF/0x10FF
0x0000 - 0x001F
0x0020 - 0x005F
0x0060 - 0x00FF
0x0100
i n t e r n a l
CPU
cycles as described in
d a t a
”General Purpose Regis-
a n d
S R A M
Figure
2 3 0 4 / 4 3 5 2
7-3.
i n
t h e
21
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