ATMEGA649P-AUR Atmel, ATMEGA649P-AUR Datasheet - Page 53
ATMEGA649P-AUR
Manufacturer Part Number
ATMEGA649P-AUR
Description
IC MCU AVR 64KB FLASH 64TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA649P-AUR
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
SPI, UART/USART, USI
Peripherals
Brown-out Detect/Reset, LCD, POR, PWM, WDT
Number Of I /o
54
Program Memory Size
64KB (32K x 16)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Manufacturer
Quantity
Price
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10.5
10.5.1
10.5.2
8284A–AVR–10/10
Register Description
MCUSR – MCU Status Register
WDTCR – Watchdog Timer Control Register
The MCU Status Register provides information on which reset source caused an MCU reset.
• Bit 4 – JTRF: JTAG Reset Flag
This bit is set if a reset is being caused by a logic one in the JTAG Reset Register selected by
the JTAG instruction AVR_RESET. This bit is reset by a Power-on Reset, or by writing a logic
zero to the flag.
• Bit 3 – WDRF: Watchdog Reset Flag
This bit is set if a Watchdog Reset occurs. The bit is reset by a Power-on Reset, or by writing a
logic zero to the flag.
• Bit 2 – BORF: Brown-out Reset Flag
This bit is set if a Brown-out Reset occurs. The bit is reset by a Power-on Reset, or by writing a
logic zero to the flag.
• Bit 1 – EXTRF: External Reset Flag
This bit is set if an External Reset occurs. The bit is reset by a Power-on Reset, or by writing a
logic zero to the flag.
• Bit 0 – PORF: Power-on Reset Flag
This bit is set if a Power-on Reset occurs. The bit is reset only by writing a logic zero to the flag.
To make use of the Reset Flags to identify a reset condition, the user should read and then
Reset the MCUSR as early as possible in the program. If the register is cleared before another
reset occurs, the source of the reset can be found by examining the Reset Flags.
• Bits 7:5 – Reserved
These bits are reserved and will always read as zero.
• Bit 4 – WDCE: Watchdog Change Enable
This bit must be set when the WDE bit is written to logic zero. Otherwise, the Watchdog will not
be disabled. Once written to one, hardware will clear this bit after four clock cycles. Refer to the
description of the WDE bit for a Watchdog disable procedure. This bit must also be set when
changing the prescaler bits.
Timer” on page 52
Bit
0x35 (0x55)
Read/Write
Initial Value
Bit
(0x60)
Read/Write
Initial Value
ATmega169A/169PA/329A/329PA/649A/649P/3290A/3290PA/6490A/6490P
R
7
–
0
7
–
R
0
R
6
–
0
R
6
–
0
”Timed Sequences for Changing the Configuration of the Watchdog
R
5
–
0
R
5
–
0
WDCE
R/W
JTRF
R/W
4
0
4
WDE
WDRF
R/W
R/W
3
0
3
See Bit Description
WDP2
R/W
BORF
R/W
2
0
2
WDP1
R/W
EXTRF
1
0
R/W
1
WDP0
R/W
PORF
0
0
R/W
0
WDTCR
MCUSR
53
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