EFM32G200F64 Energy Micro, EFM32G200F64 Datasheet - Page 434

MCU 32BIT 64KB FLASH 32-QFN

EFM32G200F64

Manufacturer Part Number
EFM32G200F64
Description
MCU 32BIT 64KB FLASH 32-QFN
Manufacturer
Energy Micro
Series
Geckor
Datasheets

Specifications of EFM32G200F64

Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
32MHz
Connectivity
EBI/EMI, I²C, IrDA, SmartCard, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
24
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.8 V
Data Converters
A/D 4x12b, D/A 1x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
32-VQFN Exposed Pad
Processor Series
EFM32G200
Core
ARM Cortex-M3
Data Bus Width
32 bit
Data Ram Size
16 KB
Interface Type
I2C, UART
Maximum Clock Frequency
32 MHz
Number Of Programmable I/os
24
Number Of Timers
2
Operating Supply Voltage
1.8 V to 3.8 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
 Details

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29.5.3 LCD_SEGEN - Segment Enable Register
29.5.4 LCD_BACTRL - Blink and Animation Control Register (Async Reg)
4
3:2
1:0
31:10
9:0
Bit
Offset
0x008
Reset
Access
Name
Bit
2010-09-06 - d0001_Rev1.00
For more information about Asynchronous Registers please see Section 5.3 (p. 18) .
WAVE
This bit configures the output waveform.
BIAS
These bits set the bias mode for the LCD Driver.
MUX
These bits set the multiplexing mode for the LCD Driver.
Reserved
SEGEN
Determines which segment lines are enabled. Each bit represents a group of 4 segment lines. To enable segment lines X to X+3,
set bit X/4, i.e. to enable output on segment lines 4,5,6 and 7, set bit 1.
Name
Name
Value
0
1
Value
0
1
2
Value
0
1
2
3
Mode
LOWPOWER
NORMAL
Mode
STATIC
ONEHALF
ONETHIRD
Mode
STATIC
DUPLEX
TRIPLEX
QUADRUPLEX
0
0x0
0x0
0x000
Reset
Reset
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
RW
RW
RW
RW
Access
Access
Description
Low power waveform
Normal waveform
Description
Static
1/2 Bias
1/3 Bias
Description
Static
Duplex
Triplex
Quadruplex
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Bit Position
Waveform Selection
Bias Configuration
Mux Configuration
Segment Enable
Description
Description
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