S9S08DN32F1MLC Freescale Semiconductor, S9S08DN32F1MLC Datasheet - Page 146
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S9S08DN32F1MLC
Manufacturer Part Number
S9S08DN32F1MLC
Description
IC MCU 8BIT 32KB FLASH 32LQFP
Manufacturer
Freescale Semiconductor
Series
HCS08r
Specifications of S9S08DN32F1MLC
Core Processor
HCS08
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, LIN, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
25
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 10x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
32-LQFP
Processor Series
S08D
Core
HCS08
Data Bus Width
8 bit
Data Ram Size
1 KB
Interface Type
I2C, SCI, SPI
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
26
Operating Supply Voltage
3 V to 5 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWS08
Development Tools By Supplier
DEMO9S08DZ60
Minimum Operating Temperature
- 40 C
On-chip Adc
12 bit, 10 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
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Price
Company:
Part Number:
S9S08DN32F1MLC
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Quantity:
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Chapter 8 Multi-Purpose Clock Generator (S08MCGV1)
8.4.7
The MCG presents the divided reference clock as MCGFFCLK for use as an additional clock source. The
MCGFFCLK frequency must be no more than 1/4 of the MCGOUT frequency to be valid. Because of this
requirement, the MCGFFCLK is not valid in bypass modes for the following combinations of BDIV and
RDIV values:
When MCGFFCLK is valid then MCGFFCLKVALID is set to 1. When MCGFFCLK is not valid then
MCGFFCLKVALID is set to 0.
8.5
This section describes how to initialize and configure the MCG module in application. The following
sections include examples on how to initialize the MCG and properly switch between the various available
modes.
8.5.1
The MCG comes out of reset configured for FEI mode with the BDIV set for divide-by-2. The internal
reference will stabilize in t
reference is stable, the FLL will acquire lock in t
Upon POR, the internal reference will require trimming to guarantee an accurate clock. Freescale
recommends using FLASH location 0xFFAE for storing the fine trim bit, FTRIM in the MCGSC register,
and 0xFFAF for storing the 8-bit trim value in the MCGTRM register. The MCU will not automatically
copy the values in these FLASH locations to the respective registers. Therefore, user code must copy these
values from FLASH to the registers.
8.5.1.1
Because the MCG comes out of reset in FEI mode, the only MCG modes which can be directly switched
to upon reset are FEE, FBE, and FBI modes (see
first configuring the MCG for one of these three initial modes. Care must be taken to check relevant status
bits in the MCGSC register reflecting all configuration changes within each mode.
To change from FEI mode to FEE or FBE modes, follow this procedure:
146
1. Enable the external clock source by setting the appropriate bits in MCGC2.
2. Write to MCGC1 to select the clock mode.
Initialization / Application Information
Fixed Frequency Clock
MCG Module Initialization Sequence
Initializing the MCG
•
•
The BDIV value should not be changed to divide-by-1 without first
trimming the internal reference. Failure to do so could result in the MCU
running out of specification.
BDIV=00 (divide by 1), RDIV < 010
BDIV=01 (divide by 2), RDIV < 011
irefst
microseconds before the FLL can acquire lock. As soon as the internal
MC9S08DN60 Series Data Sheet, Rev 3
fll_lock
NOTE
Figure
milliseconds.
8-8). Reaching any of the other modes requires
Freescale Semiconductor
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