PK30X256VMD100 Freescale Semiconductor, PK30X256VMD100 Datasheet - Page 53

• Manufacturer Part Number: PK30X256VMD100
• Description: IC ARM CORTEX MCU 256K 144-MAP
• Manufacturer: Freescale Semiconductor
• Series: Kinetisr

Specifications of PK30X256VMD100

• Core Processor: ARM Cortex-M4
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: CAN, EBI/EMI, I²C, IrDA, SDHC, SPI, UART/USART
• Peripherals: DMA, I²S, LCD, LVD, POR, PWM, WDT
• Number Of I /o: 102
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.71 V ~ 3.6 V
• Data Converters: A/D 37x16b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 144-LBGA
• Rohs Compliant: Yes
• Processor Series: Kinetis
• Core: ARM Cortex M4
• Data Ram Size: 64 KB
• Interface Type: UART, SPI, I2C, I2S, CAN
• Maximum Clock Frequency: 100 MHz
• Number Of Programmable I/os: 102
• Operating Supply Voltage: 1.71 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

6.8.1 CAN switching specifications
See
6.8.2 DSPI switching specifications (low-speed mode)
The DMA Serial Peripheral Interface (DSPI) provides a synchronous serial bus with
master and slave operations. Many of the transfer attributes are programmable. The tables
below provides DSPI timing characteristics for classic SPI timing modes. Refer to the
DSPI chapter of the Reference Manual for information on the modified transfer formats
used for communicating with slower peripheral devices.
1. The DSPI module can operate across the entire operating voltage for the processor, but to run across the full voltage
Freescale Semiconductor, Inc.
DSPI_PCSn
DSPI_SCK
(CPOL=0)
DSPI_SIN
DSPI_SOUT
range the maximum frequency of operation is reduced.
Num
DS1
DS2
DS3
DS4
DS5
DS6
DS7
DS8
General switching
Operating voltage
Frequency of operation
DSPI_SCK output cycle time
DSPI_SCK output high/low time
DSPI_PCSn to DSPI_SCK output valid
DSPI_SCK to DSPI_PCSn output hold
DSPI_SCK to DSPI_SOUT valid
DSPI_SCK to DSPI_SOUT invalid
DSPI_SIN to DSPI_SCK input setup
DSPI_SCK to DSPI_SIN input hold
Table 35. Master mode DSPI timing (low-speed mode)
Figure 22. DSPI classic SPI timing — master mode
K30 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
specifications.
DS7
DS3
Description
First data
DS8
First data
DS5
DS2
Preliminary
Data
Data
DS6
(t
(t
(t
4 x t
SCK
SCK
SCK
Peripheral operating requirements and behaviors
DS1
Last data
1.71
Min.
15
—
—
-2
0
/2) - 4
/2) - 4
/2) - 4
BCLK
Last data
(t
DS4
SCK/2)
Max.
12.5
3.6
10
—
—
—
—
—
—
+ 4
MHz
Unit
ns
ns
ns
ns
ns
ns
ns
ns
V
Notes
1
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