PK30X256VMD100 Freescale Semiconductor, PK30X256VMD100 Datasheet - Page 55

• Manufacturer Part Number: PK30X256VMD100
• Description: IC ARM CORTEX MCU 256K 144-MAP
• Manufacturer: Freescale Semiconductor
• Series: Kinetisr

Specifications of PK30X256VMD100

• Core Processor: ARM Cortex-M4
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: CAN, EBI/EMI, I²C, IrDA, SDHC, SPI, UART/USART
• Peripherals: DMA, I²S, LCD, LVD, POR, PWM, WDT
• Number Of I /o: 102
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.71 V ~ 3.6 V
• Data Converters: A/D 37x16b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 144-LBGA
• Rohs Compliant: Yes
• Processor Series: Kinetis
• Core: ARM Cortex M4
• Data Ram Size: 64 KB
• Interface Type: UART, SPI, I2C, I2S, CAN
• Maximum Clock Frequency: 100 MHz
• Number Of Programmable I/os: 102
• Operating Supply Voltage: 1.71 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Freescale Semiconductor, Inc.
DSPI_PCSn
DSPI_SCK
(CPOL=0)
DSPI_SIN
DSPI_SOUT
DS10
DS11
DS12
DS13
DS14
DS15
DS16
Num
Num
DS1
DS2
DS3
DS4
DS5
DS6
DS7
DS8
DS9
Table 37. Master mode DSPI timing (high-speed mode) (continued)
DSPI_SCK output cycle time
DSPI_SCK output high/low time
DSPI_PCSn to DSPI_SCK output valid
DSPI_SCK to DSPI_PCSn output hold
DSPI_SCK to DSPI_SOUT valid
DSPI_SCK to DSPI_SOUT invalid
DSPI_SIN to DSPI_SCK input setup
DSPI_SCK to DSPI_SIN input hold
Operating voltage
Frequency of operation
DSPI_SCK input cycle time
DSPI_SCK input high/low time
DSPI_SCK to DSPI_SOUT valid
DSPI_SCK to DSPI_SOUT invalid
DSPI_SIN to DSPI_SCK input setup
DSPI_SCK to DSIP_SIN input hold
DSPI_SS active to DSPI_SOUT driven
DSPI_SS inactive to DSPI_SOUT not driven
Table 38. Slave mode DSPI timing (high-speed mode)
Figure 24. DSPI classic SPI timing — master mode
K30 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
DS7
DS3
First data
Description
Description
DS8
First data
DS5
DS2
Preliminary
Data
Data
DS6
Peripheral operating requirements and behaviors
DS1
Last data
Last data
(t
(t
(t
(t
2 x t
SCK
SCK
SCK
4 x t
SCK
TBD
Min.
Min.
2.7
−2
—
—
—
—
/2) − 2
/2) − 2
/2) − 2
/2) − 2
0
0
2
7
DS4
BCLK
BCLK
(t
(t
SCK
SCK
Max.
Max.
TBD
12.5
8.5
3.6
14
14
—
—
—
—
—
—
—
—
—
—
/2) + 2
/2 + 2
MHz
Unit
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
V
55