PK40X256VMD100 Freescale Semiconductor, PK40X256VMD100 Datasheet - Page 20

• Manufacturer Part Number: PK40X256VMD100
• Description: IC ARM CORTEX MCU 256K 144-MAP
• Manufacturer: Freescale Semiconductor
• Series: Kinetisr

Specifications of PK40X256VMD100

• Core Processor: ARM Cortex-M4
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: CAN, EBI/EMI, I²C, IrDA, SDHC, SPI, UART/USART, USB, USB OTG
• Peripherals: DMA, I²S, LCD, LVD, POR, PWM, WDT
• Number Of I /o: 98
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.71 V ~ 3.6 V
• Data Converters: A/D 33x16b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 144-LBGA
• Rohs Compliant: YES
• Processor Series: Kinetis
• Core: ARM Cortex M4
• Data Ram Size: 64 KB
• Interface Type: UART, SPI, I2C, I2S, CAN
• Maximum Clock Frequency: 100 MHz
• Number Of Programmable I/os: 98
• Operating Supply Voltage: 1.71 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

General
5.2.2 General switching specifications
These general purpose specifications apply to all signals configured for GPIO, UART,
CAN, CMT, and I
1. The greater synchronous and asynchronous timing must be met.
2. This is the shortest pulse that is guaranteed to be recognized.
3. 75pF load
4. 15pF load
5.3 Thermal specifications
20
Symbol
GPIO pin interrupt pulse width (digital glitch filter
disabled) — Synchronous path
GPIO pin interrupt pulse width (digital glitch filter
disabled, analog filter enabled) — Asynchronous path
GPIO pin interrupt pulse width (digital glitch filter
disabled, analog filter disabled) — Asynchronous path
External reset pulse width (digital glitch filter disabled)
Mode select (EZP_CS) hold time after reset
deassertion
Port rise and fall time (high drive strength)
Port rise and fall time (low drive strength)
Description
• Slew disabled
• Slew enabled
• Slew disabled
• Slew enabled
• 1.71 ≤ V
• 2.7 ≤ V
• 1.71 ≤ V
• 2.7 ≤ V
• 1.71 ≤ V
• 2.7 ≤ V
• 1.71 ≤ V
• 2.7 ≤ V
2
C signals.
K40 Sub-Family Data Sheet Data Sheet, Rev. 5, 5/2011.
Table 10. General switching specifications
DD
DD
DD
DD
DD
DD
DD
DD
≤ 3.6V
≤ 3.6V
≤ 3.6V
≤ 3.6V
≤ 2.7V
≤ 2.7V
≤ 2.7V
≤ 2.7V
Preliminary
Min.
100
100
1.5
16
—
—
—
—
—
—
—
—
2
Max.
TBD
TBD
TBD
TBD
12
36
32
36
—
—
—
—
—
Freescale Semiconductor, Inc.
Bus clock
Bus clock
cycles
cycles
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
1
2
2
2
3
4