PK40X256VMD100 Freescale Semiconductor, PK40X256VMD100 Datasheet - Page 41

• Manufacturer Part Number: PK40X256VMD100
• Description: IC ARM CORTEX MCU 256K 144-MAP
• Manufacturer: Freescale Semiconductor
• Series: Kinetisr

Specifications of PK40X256VMD100

• Core Processor: ARM Cortex-M4
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: CAN, EBI/EMI, I²C, IrDA, SDHC, SPI, UART/USART, USB, USB OTG
• Peripherals: DMA, I²S, LCD, LVD, POR, PWM, WDT
• Number Of I /o: 98
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.71 V ~ 3.6 V
• Data Converters: A/D 33x16b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 144-LBGA
• Rohs Compliant: YES
• Processor Series: Kinetis
• Core: ARM Cortex M4
• Data Ram Size: 64 KB
• Interface Type: UART, SPI, I2C, I2S, CAN
• Maximum Clock Frequency: 100 MHz
• Number Of Programmable I/os: 98
• Operating Supply Voltage: 1.71 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

1. Typical values assume V
2. This current is a PGA module adder, in addition to and ADC conversion currents.
3. Between IN+ and IN-. The PGA draws a DC current from the input terminals. The magnitude of the DC current is a strong
4. Gain = 2
5. After changing the PGA gain setting, a minimum of 2 ADC+PGA conversions should be ignored.
6. Limit the input signal swing so that the PGA does not saturate during operation. Input signal swing is dependent on the
Freescale Semiconductor, Inc.
V
Symbol
SINAD
ENOB
SFDR
function of input common mode voltage (V
PGA reference voltage and gain setting.
PP,DIFF
SNR
THD
PGAG
Maximum
differential input
signal swing
Signal-to-noise
ratio
Total harmonic
distortion
Spurious free
dynamic range
Effective number
of bits
Signal-to-noise
plus distortion
ratio
Description
Table 28. 16-bit ADC with PGA characteristics (continued)
DDA
K40 Sub-Family Data Sheet Data Sheet, Rev. 5, 5/2011.
=3.0V, Temp=25°C, f
See ENOB
Conditions
• Gain=1
• Gain=64
• Gain=1
• Gain=64
• Gain=1
• Gain=64
• Gain=1, Average=4
• Gain=1, Average=8
• Gain=64, Average=4
• Gain=64, Average=8
• Gain=1, Average=32
• Gain=2, Average=32
• Gain=4, Average=32
• Gain=8, Average=32
• Gain=16, Average=32
• Gain=32, Average=32
• Gain=64, Average=32
CM
) and the PGA gain.
ADCK
Preliminary
=6MHz unless otherwise stated.
where V
TBD
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Min.
6.02 × ENOB + 1.76
Peripheral operating requirements and behaviors
X
= V
Typ.
83.0
57.5
89.4
90.0
90.9
77.0
12.3
12.7
13.3
13.1
12.5
11.8
11.1
10.2
8.4
8.7
9.3
REFPGA
1
× 0.583
Max.
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Unit
bits
bits
bits
bits
bits
bits
bits
bits
bits
bits
bits
dB
dB
dB
dB
dB
dB
dB
V
mode,f
Average=32,
Average=32,
Average=32
differential
differential
differential
differential
f
f
in
in
mode,
mode,
mode,
Notes
=500Hz
=500Hz
16-bit
16-bit
16-bit
16-bit
6
in
z
=100H
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