PK40N512VMD100 Freescale Semiconductor, PK40N512VMD100 Datasheet - Page 20

• Manufacturer Part Number: PK40N512VMD100
• Description: IC ARM CORTEX MCU 512K 144-MAP
• Manufacturer: Freescale Semiconductor
• Series: Kinetisr

Specifications of PK40N512VMD100

• Core Processor: ARM Cortex-M4
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: CAN, EBI/EMI, I²C, IrDA, SDHC, SPI, UART/USART, USB, USB OTG
• Peripherals: DMA, I²S, LCD, LVD, POR, PWM, WDT
• Number Of I /o: 98
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.71 V ~ 3.6 V
• Data Converters: A/D 33x16b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 144-LBGA
• Rohs Compliant: Yes
• Processor Series: Kinetis
• Core: ARM Cortex M4
• Data Ram Size: 128 KB
• Interface Type: UART, SPI, I2C, I2S, CAN
• Maximum Clock Frequency: 100 MHz
• Number Of Programmable I/os: 98
• Operating Supply Voltage: 1.71 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

General
5.2.1 Device clock specifications
5.2.2 General switching specifications
These general purpose specifications apply to all signals configured for GPIO, UART,
CAN, CMT, and I
1. The greater synchronous and asynchronous timing must be met.
2. This is the shortest pulse that is guaranteed to be recognized.
3. 75pF load
20
f
FB_CLK
FB_CLK
Symbol
Symbol
SYS_USB
f
f
FLASH
FLASH
f
f
f
f
SYS
BUS
SYS
BUS
System and core clock
System and core clock when USB in operation
Bus clock
FlexBus clock
Flash clock
System and core clock
Bus clock
FlexBus clock
Flash clock
GPIO pin interrupt pulse width (digital glitch filter
disabled) — Synchronous path
GPIO pin interrupt pulse width (digital glitch filter
disabled, analog filter enabled) — Asynchronous path
GPIO pin interrupt pulse width (digital glitch filter
disabled, analog filter disabled) — Asynchronous path
External reset pulse width (digital glitch filter disabled)
Mode select (EZP_CS) hold time after reset
deassertion
Port rise and fall time (high drive strength)
Port rise and fall time (low drive strength)
Description
Description
• Slew disabled
• Slew enabled
• Slew disabled
• Slew enabled
2
C signals.
K40 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
Normal run mode
Preliminary
VLPR mode
TBD
Min.
Min.
100
1.5
20
16
—
—
—
—
—
—
—
—
—
—
—
—
2
Max.
Max.
100
50
50
25
12
36
32
36
—
—
—
—
—
—
2
2
2
1
Freescale Semiconductor, Inc.
Bus clock
Bus clock
cycles
cycles
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
Unit
Unit
ns
ns
ns
ns
ns
ns
Notes
Notes
1
2
3
4
2