PK40N512VMD100 Freescale Semiconductor, PK40N512VMD100 Datasheet - Page 43

• Manufacturer Part Number: PK40N512VMD100
• Description: IC ARM CORTEX MCU 512K 144-MAP
• Manufacturer: Freescale Semiconductor
• Series: Kinetisr

Specifications of PK40N512VMD100

• Core Processor: ARM Cortex-M4
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: CAN, EBI/EMI, I²C, IrDA, SDHC, SPI, UART/USART, USB, USB OTG
• Peripherals: DMA, I²S, LCD, LVD, POR, PWM, WDT
• Number Of I /o: 98
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.71 V ~ 3.6 V
• Data Converters: A/D 33x16b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 144-LBGA
• Rohs Compliant: Yes
• Processor Series: Kinetis
• Core: ARM Cortex M4
• Data Ram Size: 128 KB
• Interface Type: UART, SPI, I2C, I2S, CAN
• Maximum Clock Frequency: 100 MHz
• Number Of Programmable I/os: 98
• Operating Supply Voltage: 1.71 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Freescale Semiconductor, Inc.
Symbol
SINAD
ENOB
SFDR
DNL
THD
Table 25. 16-bit ADC characteristics (V
INL
E
E
FS
Q
Differential non-
linearity
Integral non-
linearity
Full-scale error
Quantization
error
Effective number
of bits
Signal-to-noise
plus distortion
Total harmonic
distortion
Spurious free
dynamic range
Description
K40 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
16 bit differential mode
16 bit single-ended mode
See ENOB
16 bit differential mode
16 bit single-ended mode
16 bit differential mode
16 bit single-ended mode
Conditions
• ≤13 bit modes
• <12 bit modes
• ≤13 bit modes
• <12 bit modes
• ≤13 bit modes
• <12 bit modes
• 16 bit modes
• ≤13 bit modes
• Avg=32
• Avg=1
• Avg=32
• Avg=1
• Avg=32
• Avg=32
• Avg=32
• Avg=32
1
Table continues on the next page...
Preliminary
REFH
TBD
TBD
TBD
TBD
TBD
TBD
Min.
= V
—
—
—
—
—
—
—
—
6.02 × ENOB + 1.76
DDA
Peripheral operating requirements and behaviors
, V
-1 to 0
Typ.
±0.7
±0.2
±1.0
±0.5
±0.4
±1.0
13.6
13.2
TBD
TBD
TBD
TBD
-94
REFL
95
—
2
= V
±TBD
±TBD
±TBD
±TBD
±TBD
SSA
Max.
TBD
TBD
TBD
TBD
TBD
TBD
±0.5
±0.5
—
—
—
) (continued)
LSB
LSB
LSB
LSB
Unit
bits
bits
bits
bits
dB
dB
dB
dB
dB
4
4
4
4
conversion
%1, AVGS
averaging
averaging
hardware
<12MHz,
(AVGE =
V
= %11)
Notes
clock
V
ADC
Max
Max
ADIN
DDA
5
5
5
=
43