PK40N512VMD100 Freescale Semiconductor, PK40N512VMD100 Datasheet - Page 36

• Manufacturer Part Number: PK40N512VMD100
• Description: IC ARM CORTEX MCU 512K 144-MAP
• Manufacturer: Freescale Semiconductor
• Series: Kinetisr

Specifications of PK40N512VMD100

• Core Processor: ARM Cortex-M4
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: CAN, EBI/EMI, I²C, IrDA, SDHC, SPI, UART/USART, USB, USB OTG
• Peripherals: DMA, I²S, LCD, LVD, POR, PWM, WDT
• Number Of I /o: 98
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.71 V ~ 3.6 V
• Data Converters: A/D 33x16b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 144-LBGA
• Rohs Compliant: Yes
• Processor Series: Kinetis
• Core: ARM Cortex M4
• Data Ram Size: 128 KB
• Interface Type: UART, SPI, I2C, I2S, CAN
• Maximum Clock Frequency: 100 MHz
• Number Of Programmable I/os: 98
• Operating Supply Voltage: 1.71 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Peripheral operating requirements and behaviors
6.4.2 EzPort Switching Specifications
6.4.3 Flexbus Switching Specifications
All processor bus timings are synchronous; input setup/hold and output delay are given in
respect to the rising edge of a reference clock, FB_CLK. The FB_CLK frequency may be
the same as the internal system bus frequency or an integer divider of that frequency.
36
EZP_CK
EZP_CS
EZP_Q (output)
EZP_D (input)
EP1a
Num
EP1
EP2
EP3
EP4
EP5
EP6
EP7
EP8
EP9
Operating voltage
EZP_CK frequency of operation (all commands except
READ)
EZP_CK frequency of operation (READ command)
EZP_CS negation to next EZP_CS assertion
EZP_CS input valid to EZP_CK high (setup)
EZP_CK high to EZP_CS input invalid (hold)
EZP_D input valid to EZP_CK high (setup)
EZP_CK high to EZP_D input invalid (hold)
EZP_CK low to EZP_Q output valid (setup)
EZP_CK low to EZP_Q output invalid (hold)
EZP_CS negation to EZP_Q tri-state
Description
K40 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
Table 22. EzPort switching specifications
EP3
Figure 10. EzPort Timing Diagram
EP5
EP6
EP4
EP7
Preliminary
EP8
EP9
EP2
2 x t
Min.
2.7
—
—
EZP_CK
—
—
5
5
2
5
0
Freescale Semiconductor, Inc.
f
f
Max.
SYS
SYS
3.6
12
12
—
—
—
—
—
—
/2
/8
MHz
MHz
Unit
ns
ns
ns
ns
ns
ns
ns
ns
V