PK40N512VMD100 Freescale Semiconductor, PK40N512VMD100 Datasheet - Page 58

• Manufacturer Part Number: PK40N512VMD100
• Description: IC ARM CORTEX MCU 512K 144-MAP
• Manufacturer: Freescale Semiconductor
• Series: Kinetisr

Specifications of PK40N512VMD100

• Core Processor: ARM Cortex-M4
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: CAN, EBI/EMI, I²C, IrDA, SDHC, SPI, UART/USART, USB, USB OTG
• Peripherals: DMA, I²S, LCD, LVD, POR, PWM, WDT
• Number Of I /o: 98
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.71 V ~ 3.6 V
• Data Converters: A/D 33x16b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 144-LBGA
• Rohs Compliant: Yes
• Processor Series: Kinetis
• Core: ARM Cortex M4
• Data Ram Size: 128 KB
• Interface Type: UART, SPI, I2C, I2S, CAN
• Maximum Clock Frequency: 100 MHz
• Number Of Programmable I/os: 98
• Operating Supply Voltage: 1.71 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Peripheral operating requirements and behaviors
6.8.6 DSPI switching specifications (high-speed mode)
The DMA Serial Peripheral Interface (DSPI) provides a synchronous serial bus with
master and slave operations. Many of the transfer attributes are programmable. The tables
below provide DSPI timing characteristics for classic SPI timing modes. Refer to the
DSPI chapter of the Reference Manual for information on the modified transfer formats
used for communicating with slower peripheral devices.
58
DSPI_PCSn
DSPI_SCK
(CPOL=0)
DSPI_SIN
DSPI_SOUT
DS10
Num
Num
DS1
DS2
DS3
DS4
DS5
DS6
DS7
DS8
DS9
Operating voltage
Frequency of operation
DSPI_SCK output cycle time
DSPI_SCK output high/low time
DSPI_PCSn to DSPI_SCK output valid
DSPI_SCK to DSPI_PCSn output hold
DSPI_SCK to DSPI_SOUT valid
DSPI_SCK to DSPI_SOUT invalid
DSPI_SIN to DSPI_SCK input setup
DSPI_SCK to DSPI_SIN input hold
Operating voltage
Frequency of operation
DSPI_SCK input cycle time
DSPI_SCK input high/low time
Table 39. Master mode DSPI timing (high-speed mode)
Table 40. Slave mode DSPI timing (high-speed mode)
Figure 24. DSPI classic SPI timing — master mode
K40 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
DS7
DS3
First data
Description
Description
DS8
First data
Table continues on the next page...
DS5
DS2
Preliminary
Data
Data
DS6
DS1
Last data
Last data
(t
(t
(t
(t
2 x t
SCK
SCK
SCK
4 x t
SCK
TBD
Min.
Min.
2.7
2.7
−2
—
—
/2) − 2
/2) − 2
/2) − 2
/2) − 2
0
DS4
BCLK
BCLK
Freescale Semiconductor, Inc.
(t
(t
SCK
SCK
Max.
Max.
12.5
3.6
8.5
3.6
25
—
—
—
—
—
—
—
/2) + 2
/2 + 2
MHz
MHz
Unit
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
V
V