SPEAR310-2 STMicroelectronics, SPEAR310-2 Datasheet
SPEAR310-2
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SPEAR310-2 Summary of contents
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... The SPEAr310 embedded MPU is configurable for a range of telecom and networking applications such as: ■ Routers, switches and gateways ■ Remote apparatus control ■ Metering concentrators Table 1. Order code SPEAR310-2 Doc ID 16482 Rev 2 SPEAr310 LFBGA289 ( 1.7 mm) Device summary Temp Package Packing range, ° C LFBGA289 - (15x15 mm, pitch 0 ...
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... Clock and reset system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Power saving system mode control . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Vectored interrupt controller (VIC General purpose timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 RTC oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 UART with hardware flow control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 UARTs with software flow control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 TDM interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 E1 interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 HDLC controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Doc ID 16482 Rev 2 SPEAr310 ...
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... SPEAr310 2.19 USB2 device controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 2.20 Cryptographic co-processor (C3 2.21 JPEG CODEC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.1 Required external components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.2 Dedicated pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.3 Shared I/O pins (PL_GPIOs 3.3.1 3.3.2 3.3.3 3.3.4 3.3.5 3.3.6 3.4 PL_GPIO pin sharing for debug modes . . . . . . . . . . . . . . . . . . . . . . . . . . 37 4 Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 5 Electrical characteristics ...
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... Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 8 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 4/72 8-bit NAND Flash configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 16-bit NAND Flash configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 MII transmit timing specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 MII receive timing specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 MDIO timing specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 SPI master mode timings (clock phase = SPI master mode timings (clock phase = Doc ID 16482 Rev 2 SPEAr310 ...
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... DDR pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Table 9. PL_GPIO pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Table 10. PL_GPIO multiplexing scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Table 11. Table shading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Table 12. Ball sharing during debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Table 13. SPEAr310 memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Table 14. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Table 15. Maximum power consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Table 16. Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Table 17. Overshoot and undershoot specifications Table 18. ...
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... List of tables Table 47. UART receive timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Table 48. LFBGA289 ( 1.7 mm) mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Table 49. Thermal resistance characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Table 50. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 6/72 Doc ID 16482 Rev 2 SPEAr310 ...
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... SPEAr310 List of figures Figure 1. Functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Figure 2. Typical system architecture using SPEAr310 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Figure 3. Clock generator overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Figure 4. Typical SMII system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Figure 5. Hierarchical multiplexing scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Figure 6. Power-up sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Figure 7. Power-down sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Figure 8. DDR2 Read cycle waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Figure 9. DDR2 Read cycle path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Figure 10 ...
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... Description 1 Description The SPEAr310 is a member of the SPEAr family of embedded MPUs, optimized for telecom applications based on the powerful ARM926EJ-S processor (up to 333 MHz), widely used in applications where high computation performance is required. In addition, SPEAr310 has an MMU that allows virtual memory management -- making the system compliant with advanced operating systems, like Linux ...
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... SPEAr310 ● ARM926EJ-S 32-bit RISC CPU 333 MHz – 16 Kbytes of instruction cache, 16 Kbytes of data cache – 3 instruction sets: 32-bit for high performance, 16-bit (Thumb) for efficient code density, Java mode (Jazelle™) for direct execution of Java bytecode. – AMBA bus interface ● ...
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... JTAG IEEE 1149.1 ● Boundary scan ● ETM functionality multiplexed on primary pins ● Supply voltages – 1.2 V core, 1.8 V/2.5 V DDR, 2.5 V PLLs, 1.5 V RTC and 3.3 V I/Os ● Operating temperature °C ● LFBGA289 ( mm, pitch 0.8 mm) 10/72 Doc ID 16482 Rev 2 SPEAr310 ...
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... Typical system architecture using SPEAr310 2.1 CPU ARM 926EJ-S The core of the SPEAr310 is an ARM926EJ-S reduced instruction set computer (RISC) processor. It supports the 32-bit ARM and 16-bit Thumb instruction sets, enabling the user to trade off between high performance and high code density and includes features for efficient execution of Java byte codes ...
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... DDR_CLK @ 100-333 MHz for DDR memory interface. The default values give the maximum allowed clock frequencies. The clock frequencies are fully programmable through dedicated registers. The clock system consists of 2 main parts: a multi clock generator block and three internal PLLs. 12/72 3). Doc ID 16482 Rev 2 SPEAr310 ...
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... MHz or a sub-multiple (/2, /4, /8). 2.2.2 Power saving system mode control Using three mode control bits, the system controller switch the SPEAr310 to any one of four different modes: DOZE, SLEEP, SLOW and NORMAL. ● SLEEP mode: In this mode the system clocks, HCLK and CPU_CLK, are disabled and the System Controller clock is driven by a low speed oscillator (nominally 32768 Hz) ...
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... General purpose timers SPEAr310 provides three general purpose timers (GPTs) acting as APB slaves. The timers can capture input signals from external pins (enabled as PL_GPIO alternate functions). Each GPT consists of 2 channels, each one made programmable 16-bit counter and a dedicated 8-bit timer clock prescaler ...
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... Isolation mode, allowing RTC to work even if power is not supplied to the rest of the device. 2.3 Multichannel DMA controller Within its basic subsystem, SPEAr310 provides an DMA controller (DMAC) able to service independent DMA channels for sequential data transfers between single source and destination (i.e., memory-to-memory, memory-to-peripheral, peripheral to- memory, and peripheral-to-peripheral). ...
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... Supports single asynchronous transfers. ● Supports peripherals which use Byte Lane procedure 2.8 Flexible static memory controller (FSMC) SPEAr310 provides a Flexible Static Memory Controller (FSMC) which interfaces the AHB bus to external parallel NAND Flash memories. 16/72 Doc ID 16482 Rev 2 SPEAr310 ...
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... Only chips selects are unique for each peripheral. ● External asynchronous wait control. 2.9 UARTs The SPEAr310 has 5 UARTs featuring software flow control and 1 UART featuring hardware and/or software flow control. 2.9.1 UART with hardware flow control Main features: ● ...
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... Architecture overview 2.10 Synchronous serial port (SSP) SPEAr310 provides one synchronous serial port (SSP) block that offers a master or slave interface to enables synchronous serial communication with slave or master peripherals. Main features: ● Master or slave operation. ● Programmable clock bit rate and prescale. ...
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... SPEAr310 2.12 TDM/E1 HDLC controller SPEAr310 features a TDM/E1 HDLC controller which is composed of two main blocks: Time Division Multiplexing (TDM) and High-level Data Link Control (HDLC) engines. The internal HDLC controller can service up to 128 Tx/Rx channels simultaneously in conventional HDLC mode and supports super-channel configuration. Each channel bit rate is programmable from 4 kbit kbit/s ...
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... A maximum of 102 GPIOs are available when part of the embedded IPs are not needed (see "Pin description" table). Within its basic subsystem, SPEAr310 provides twelve General Purpose Input/Output (GPIO) block. Each GPIO block provides 8 programmable inputs or outputs. Main features of the GPIO are: ● ...
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... Programmable auto scan for all the eight channels. 2.16 SMII Ethernet controller SPEAr310 features four Ethernet MACs providing SMII interfaces. Each MAC channel has dedicated TX/RX signals while synchronization and clock signals are common for PHY connection. Figure 4 shows the typical SMII configuration (a generic example with four ports): Figure 4 ...
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... Configurable Endianess for the DMA Interface (AHB Master) 2.17 MII Ethernet controller SPEAr310 provides an Ethernet MAC 10/100 Universal (commonly referred to as GMAC- UNIV), enabling to transmit and receive data over Ethernet in compliance with the IEEE 802.3-2002 standard. Note: GMAC is a hardware block implementing Ethernet MAC layer 2 processing. GMAC is configured for 10/100 Mbps operation on SPEAr3xx family and Gbps on SPEAr600 ...
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... It supports both big-endian and little-endian. 2.18 USB2 host controller SPEAr310 has two fully independent USB 2.0 hosts. Each consists of 5 major blocks: ● EHCI capable of managing high-speed transfers (HS mode, 480 Mbps) ● OHCI that manages the full and the low speed transfers (12 Mbps) ● ...
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... A USB plug (UPD) detects the connection of a cable. 2.20 Cryptographic co-processor (C3) SPEAr310 has an embedded Channel Control Coprocessor (C3 high-performance instruction driven DMA based co-processor. It executes instruction flows generated by the host processor. After it has been set-up by the host it runs in a completely autonomous way (DMA data in, data processing, DMA data out), until the completion of all the requested operations ...
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... SPEAr310 2.21 JPEG CODEC SPEAr310 provides a JPEG CODEC with header processing (JPGC), able to decode (or encode) image data contained in the SPEAr310 RAM, from the JPEG (or MCU) format to the MCU (or JPEG) format. Main features: ● Compliance with the baseline JPEG standard (ISO/IEC 10918-1) ● ...
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... Pin description 3 Pin description The following tables describe the pinout of the SPEAr310 listed by functional block. List of abbreviations Pull Pull Down 3.1 Required external components ● DDR_COMP_1V8: place an external 121 kΩ resistor between ball P4 and ball R4 ● USB_TX_RTUNE: connect an external 43.2 kΩ pull-down resistor to ball K5 ● ...
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... SPEAr310 Table 3. Power supply pin description (continued) Group ANALOG GROUND I/O CORE USB HOST0 PHY USB HOST1 PHY USB DEVICE PHY USB_HOST1_HOST0_DEVICE_DVDD1V2 OSCI (master clock) PLL1 PLL2 DDR I/O ADC OSCI RTC Note: All the VDD 2V5 power supplies are analog VDD. ...
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... Serial Flash chip select Function USB Device D+ I/O analog buffer 5 V USB Device D- USB Device TTL input buffer Input VBUS 3.3 V tolerant, PD SPEAr310 Pin type TTL Schmitt trigger input buffer, 3.3 V tolerant TTL Schmitt trigger input buffer, 3.3 V tolerant, PU Pin type ...
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... SPEAr310 Table 6. USB pin descriptions (continued) Group Signal name USB_HOST1_DP USB_HOST1_DM USB_HOST1_VBUS USB_HOST1_OVERCUR USB HOST USB_HOST0_DP USB_HOST0_DM USB_HOST0_VBUS USB_HOST0_OVERCUR USB_TXRTUNE USB USB_ANALOG_TEST Table 7. ADC pin description Group ADC ADC_VREFN ADC_VREFP Ball Direction Signal name Ball Direction AIN_0 N16 AIN_1 N15 AIN_2 ...
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... Output Bank select R8 U8 Output Row Add. Strobe T8 Output Col. Add. Strobe T7 Output Write enable U7 Output Clock enable T9 Output Differential clock U9 P9 Output Chip Select R9 T3 On-Die I/O Termination T4 Enable lines Doc ID 16482 Rev 2 SPEAr310 Pin type SSTL_2/SSTL_1 8 Differential SSTL_2/SSTL_1 8 SSTL_2/SSTL_1 8 ...
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... SPEAr310 Table 8. DDR pin description (continued) Group Signal name DDR_MEM_DQ_0 DDR_MEM_DQ_1 DDR_MEM_DQ_2 DDR_MEM_DQ_3 DDR_MEM_DQ_4 DDR_MEM_DQ_5 DDR_MEM_DQ_6 DDR_MEM_DQ_7 DDR_MEM__DQS_0 nDDR_MEM_DQS_0 DDR_MEM_DM_0 DDR_MEM_GATE_O DDR_MEM_DQ_8 DDR_MEM_DQ_9 DDR_MEM_DQ_10 DDR DDR_MEM_DQ_11 DDR_MEM_DQ_12 DDR_MEM_DQ_13 DDR_MEM_DQ_14 DDR_MEM_DQ_15 DDR_MEM_DQS_1 nDDR_MEM_DQS_1 DDR_MEM_DM_1 DDR_MEM_GATE_O DDR_MEM_VREF DDR_MEM_COMP2 V5_GNDBGCOMP DDR_MEM_COMP2 V5_REXT DDR2_EN Ball ...
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... Configuration modes RAS normal or RAS GPIO mode is selected by programming the RAS control registers. Details of each PL_GPIO pin are given in page 34 RAS normal mode is the default mode for SPEAr310. It mainly provides: ● External Memory Interface (16 data bits, 24 address bits and 4 chip selects) ● ...
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... The output multiplexer is controlled by the Function enable register and allows you to enable the alternate function of the embedded IPs, see column “Alternate function (enabled by Function Enable register)” get more information about these registers, please refer to the SPEAr310 user manual. and can be individually enabled/disabled via RAS control Figure 5 are controlled by different registers ...
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... ETH0_TX ETH0_RX ETH1_TX ETH1_RX ETH2_TX ETH2_RX ETH3_TX ETH3_RX ETH_SYNC SMII_MDIO SMII_MDC EMI_ADDB_0/FSMC_D0 EMI_ADDB_1/FSMC_D1 EMI_ADDB_2/FSMC_D2 EMI_ADDB_3/FSMC_D3 EMI_ADDB_4/FSMC_D4 EMI_ADDB_5/FSMC_D5 EMI_ADDB_6/FSMC_D6 Doc ID 16482 Rev 2 SPEAr310 Alternate Function in Boot RAS GPIO by Function pins mode GPIO12_7 GPIO12_6 GPIO12_5 GPIO12_4 GPIO12_3 GPIO12_2 GPIO12_1 GPIO12_0 GPIO11_7 GPIO11_6 GPIO11_5 ...
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... SPEAr310 Table 10. PL_GPIO multiplexing scheme (continued pin number PL_GPIO_79/F14 PL_GPIO_78/D15 PL_GPIO_77/B17 PL_GPIO_76/F13 PL_GPIO_75/E14 PL_GPIO_74/C16 PL_GPIO_73/A17 PL_GPIO_72/B16 PL_GPIO_71/D14 PL_GPIO_70/C15 PL_GPIO_69/A16 PL_GPIO_68/B15 PL_GPIO_67/C14 PL_GPIO_66/E13 PL_GPIO_65/B14 PL_GPIO_64/D13 PL_GPIO_63/C13 PL_GPIO_62/A15 PL_GPIO_61/E12 PL_GPIO_60/A14 PL_GPIO_59/B13 PL_GPIO_58/D12 PL_GPIO_57/E11 PL_GPIO_56/C12 PL_GPIO_55/A13 PL_GPIO_54/E10 PL_GPIO_53/D11 PL_GPIO_52/B12 PL_GPIO_51/D10 PL_GPIO_50/A12 PL_GPIO_49/C11 PL_GPIO_48/B11 PL_GPIO_47/C10 ...
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... RS0_OUT RS0_RXCLK RS0_TXCLK RS0_CTS RS1_IN MII_RX_ERR RS1_OUT RS1_RXCLK RS1_TXCLK RS1_CTS TDM0_DTOUT TDM0_RSYNC TDM0_TSYNC TDM0_DTIN SSP_MOSI SSP_SCLK SSP_SS0 SSP_MISO Doc ID 16482 Rev 2 SPEAr310 Alternate Function in Boot RAS GPIO pins mode UART0_DTR GPIO6_0 UART0_RI GPIO5_7 UART0_DSR GPIO5_6 GPIO5_5 UART0_CTS GPIO5_4 UART0_RTS GPIO5_3 SSP_CS4 ...
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... SSP I2C Note: For the full description of the I/O functions related to each IP, please refer to the corresponding sections of the SPEAR310 user manual. 3.4 PL_GPIO pin sharing for debug modes In some cases the PL_GPIO pins may be used in different ways for debugging purposes. There are three different cases (see also ...
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... Functional I/O BSR Value Functional I/O BSR Value Functional I/O BSR Value Functional I/O BSR Value Functional I/O BSR Value Functional I/O BSR Value Functional I/O Doc ID 16482 Rev 2 SPEAr310 debug, are used 0/1 0/1 0 nTRST_ARM TCK_ARM TSM_ARM TDI_ARM TDO_ARM ARM_TRACE_CLK ARM_TRACE_PKTA[0] ...
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... SPEAr310 Table 12. Ball sharing during debug (continued) Signal PL_GPIO[81] PL_GPIO[80] PL_GPIO[79] PL_GPIO[78] PL_GPIO[77] PL_GPIO[76] PL_GPIO[75] PL_GPIO[74] PL_GPIO[73] PL_GPIO[72:0] Case 1 - Board Debug Case 2 - Static Debug Case 3 - Full Debug BSR Value Functional I/O BSR Value Functional I/O BSR Value Functional I/O BSR Value ...
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... Memory map 4 Memory map Table 13. SPEAr310 memory mapping Start address 0x0000_0000 0x4000_0000 0x4400_0000 0x4500_0000 0x4F00_0000 0x5000_0000 0x6000_0000 0x7000_0000 0x8000_0000 0x9000_0000 0xA000_0000 0xB000_0000 0xB080_0000 0xB100_0000 0xB180_0000 0xB200_0000 0xB208_0000 0xB210_0000 0xB218_0000 0xB220_0000 0xB228_0000 0xB280_0000 0xB300_0000 0xB380_0000 0xB400_0000 0xB480_0000 0xD000_0000 0xD008_0000 0xD010_0000 40/72 End address ...
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... SPEAr310 Table 13. SPEAr310 memory mapping (continued) Start address 0xD018_0000 0xD020_0000 0xD080_0000 0xD100_0000 0xD180_0000 0xD280_0000 0xD800_0000 0xE080_0000 0xE100_0000 0xE110_0000 0xE120_0000 0xE130_0000 0xE180_0000 0xE190_0000 0xE1A0_0000 0xE210_0000 0xE220_0000 0xE280_0000 0xE290_0000 0xF000_0000 0xF010_0000 0xF110_0000 0xF120_0000 0xF800_0000 0xFC00_0000 0xFC20_0000 0xFC40_0000 0xFC60_0000 0xFC80_0000 0xFC88_0000 0xFC90_0000 End address ...
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... Memory map Table 13. SPEAr310 memory mapping (continued) Start address 0xFC98_0000 0xFCA0_0000 0xFCA8_0000 0xFCB0_0000 0xFCB8_0000 0xFF00_0000 42/72 End address Peripheral 0xFC9F_FFFF General Purpose I/O 0xFCA7_FFFF System Controller 0xFCAF_FFFF MISC (Miscellaneous) 0xFCB7_FFFF Timer 3 0xFEFF_FFFF 0xFFFF_FFFF Internal ROM Doc ID 16482 Rev 2 SPEAr310 Description GPIO configuration registers ...
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... SPEAr310 5 Electrical characteristics 5.1 Absolute maximum ratings This product contains devices to protect the inputs against damage due to high/low static voltages. However it is advisable to take normal precaution to avoid application of any voltage higher/lower than the specified maximum/minimum rated voltages. The absolute maximum rating is the maximum stress that can be applied to a device without causing permanent damage ...
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... Parameter Supply voltage for the core Supply voltage for the I/Os Supply voltage for the analog blocks Supply voltage for DRAM interface RTC supply voltage Case temperature Parameter Amplitude Doc ID 16482 Rev 2 SPEAr310 Min Typ Max Unit 1.14 1.2 1 3.3 3 ...
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... SPEAr310 5.5 3.3V I/O characteristics The 3.3 V I/Os are compliant with JEDEC standard JESD8b Table 18. Low voltage TTL DC input specification (3 V< V Symbol hyst Table 19. Low voltage TTL DC output specification (3 V< V Symbol V Low level output voltage OL V High level output voltage OH 1. For the max current value (X mA) refer to Table 20 ...
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... Parameter Voltage applied to core/pad and finally V 1.8, then V 2 Power-up sequence V 2.5 DD Doc ID 16482 Rev 2 Min Typ Max 75 150 Min Typ Max 0.49 * 0.500 * 0. DDE DDE DDE Figure . V 3.3 DD Figure supply, followed by the V 1.8 DD SPEAr310 Unit Ω Ω Unit 1 supply and ...
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... SPEAr310 Figure 7. Power-down sequence 3.3 DD 5.9 Power on reset (MRESET) The MRESET must remain active for at least 10 ms after all the power supplies are in the correct range and should become active in no more than 10 µs when one of the power supplies goes out of the correct range. ...
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... DDR2 Read cycle waveforms DQS DQ Figure 9. DDR2 Read cycle path DQ DQS Table 25. DDR2 Read cycle timings Frequency 333 MHz 266 MHz 200 MHz 48/ DLL t4 max 1.24 ns 1.43 ns 1.74 ns Doc ID 16482 Rev 2 SPEAr310 = 125° C and in best case SET CLR t5 max -495 ps -306 ...
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... SPEAr310 Table 25. DDR2 Read cycle timings (continued) Frequency 166 MHz 133 MHz 6.1.2 DDR2 write cycle timings Figure 10. DDR2 Write cycle waveforms CLK DQS t4 DQ Figure 11. DDR2 Write cycle path Table 26. DDR2 Write cycle timings Frequency 333 MHz 266 MHz 200 MHz ...
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... ADDRESS, STROBEs, AND CONTROL LINES Figure 13. DDR2 Command path Table 27. DDR2 Command timings Frequency 333 MHz 266 MHz 200 MHz 166 MHz 133 MHz 50/ max t5 max 1.39 1.40 1.77 1.78 2.39 2.40 2.90 2.91 3.65 3.66 Doc ID 16482 Rev 2 SPEAr310 Unit ...
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... SPEAr310 2 6 timing characteristics The characterization timing is done considering an output load SCL and SDA. The operating conditions are best case. 2 Figure 14 output pins HCLK 2 Figure 15 input pins The flip-flops used to capture the incoming signals are re-synchronized with the AHB clock (HCLK): so, no input delay calculation is required ...
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... C in standard speed mode Parameter t SU-STA t HD-STA t SU-DAT t HD-DAT t SU-STO t HD-STO Doc ID 16482 Rev 2 and t ) are programmable. SCLLow Min 157.5897 325.9344 314.0537 0.7812 637.709 4742.1628 Min 637.5897 602.169 1286.0537 0.7812 637.709 4742.1628 Min 4723.5897 3991.9344 4676.0537 0.7812 4027.709 4742.1628 SPEAr310 Unit ns Unit ns Unit ns ...
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... I C controller of SPEAr310 is one-clock cycle based (6 ns with the HCLK clock at 166 MHz). This time may be insufficient for some slave devices. A few slave devices may not receive the valid address due to the lack of SDA hold time and will not acknowledge even if the address is valid ...
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... Figure 19. Input pads for 8-bit NAND Flash configuration .. ..2 2 Figure 20. Output command signal waveforms for 8-bit NAND Flash configuration NFCE NFCLE NFWE NFIO 54/72 D SET CLR ... ... D CLR .. CLE Command Doc ID 16482 Rev ... NFRWPRT SET Q NFIO_0..7 Q SPEAr310 NFCLE NFCE NFWE NFRE NFALE ...
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... SPEAr310 Figure 21. Output address signal waveforms for 8-bit NAND Flash configuration NFCE NFALE NFWE NFIO Figure 22. In/out data address signal waveforms for 8-bit NAND Flash configuration NFCE NFWE NFIO (out) NFRE NFIO (in) Table 32. Time characteristics for 8-bit NAND Flash configuration Parameter ...
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... Figure 25. Output command signal waveforms 16-bit NAND Flash configuration NFCE NFCLE NFWE NFIO 56/72 D SET Q Q CLR ... ... D SET Q Q CLR CLE Command Doc ID 16482 Rev 2 SPEAr310 NFCLE NFCE NFWE NFRE NFRWPRT NFALE NFIO_0..7 CLPOWER ... CLLP CLLE (NFIO_8..15) CLFP CLCP CLAC CLD_23.. ... ...
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... SPEAr310 Figure 26. Output address signal waveforms 16-bit NAND Flash configuration NFCE NFALE NFWE NFIO Figure 27. In/out data signal waveforms for 16-bit NAND Flash configuration NFCE NFWE NFIO (out) NFRE NFIO (in) Table 33. Time characteristics for 16-bit NAND Flash configuration Parameter TCLE TALE ...
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... Value using MII 100 MHz 6.8 ns 2.9 ns 33.2 ns value for the PHY you have to consider the next t SETUP SETUP Doc ID 16482 Rev 2 Tf MII_TX[0..3], t2 MII_TXEN, MII_TXER MII_TXCLK Value using MII 2.5 MHz 6.8 ns 2.9 ns 393.2 ns rising edge, so CLK = CLK max SPEAr310 Tr ...
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... SPEAr310 6.4.2 MII receive timing specifications Figure 30. MII RX waveforms MII_RXCLK MII_RXD0-MII_RXD3, MII_RXER, MII_RXDV Figure 31. Block diagram of MII RX pins M II_R X[0..3], M II_R II_R II_R 6.4.3 MDIO timing specifications Figure 32. MDC waveforms MDC Input MDIO Output Tclock Tclock Tsetup Thold Tmax Tmi n ...
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... When MDIO is used as output the data are launched on the falling edge of the clock as shown in Figure 32. 60/ SET OUTPUT SET Value 614.4 ns 1.18 ns 1.14 ns Output 307 ns 307 ns Input - t3 6.88 ns min -1.54 ns max Doc ID 16482 Rev 2 SPEAr310 t1 t2 MDIO MDC Frequency 1.63 MHz ...
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... SPEAr310 6.5 SMI - Serial memory interface timing characteristics Figure 34. SMI_DATAIN data path Table 36. SMI_DATAIN timings Signal SMI_DATAIN Figure 35. SMI_DATAOUT/SMI_CSn data paths OUTPUT SMICLK t t input_delay D SMI_DATAIN SMI_CLK_i t CD SMI_CLK t SMIDATAIN arrival Parameter t d_max t d_min t cd_min t cd_max t SETUP_max t HOLD_min Doc ID 16482 Rev 2 ...
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... SMI_DATAOUT timings Signal SMI_DATAOUT Figure 37. SMICSn fall timings Table 38. SMI_CSn fall timings Signal SMI_CSn fall 62/ delay_min delay_max Parameter t t delay_max arrivalSMIDATAOUT_max t t delay_min arrivalSMIDATAOUT_min Parameter t t delay_max arrivalSMICSn_max_fall t t delay_min arrivalSMICSn_min_fall Doc ID 16482 Rev 2 SPEAr310 t arrival Value - t arrival_SMI_CLK_min - t arrival_SMI_CLK_max Value - t arrival_SMI_CLK_min_fall - t arrival_SMI_CLK_max_fall ...
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... SPEAr310 Figure 38. SMI_CSn rise timings Table 39. SMI_CSn rise timings Signal SMI_CSn rise Table 40. Timing requirements for SMI Parameter SMI_CLK SMIDATAIN SMIDATAOUT Output valid time SMICS_0 Output valid time SMICS_1Output valid time Parameter t t delay_max arrivalSMICSn_max_rise t t delay_min arrivalSMICSn_min_rise Input setup-hold/output delay ...
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... T = Tc(CLK) = SSP_CLK period is equal to the SSP module master clock divided by a configurable divider. Figure 39. SSP_CLK timings 64/72 Parameters T Cycle time, SSP_CLK c(CLK) T Pulse duration, SSP_CLK high w(CLKH) T Pulse duration, SSP_CLK low w(CLKL) Doc ID 16482 Rev 2 SPEAr310 Value Unit 24 ns 0.49T - 0.51T ns 0.51T - 0.49T ns ...
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... SPEAr310 6.6.1 SPI master mode timings (clock phase = 0) Table 42. Timing requirements for SPI master mode (clock phase = 0) No su(DIV-CLKL su(DIV-CLKH h(CLKL-DIV h(CLKH-DIV 1/SSP_CLK in nanoseconds (ns). For example, if the SSP_CLK frequency is 83 MHz, use P = 12.048 ns Table 43. Switching characteristics over recommended operating conditions for SPI master mode (clock phase = 0) No ...
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... Parameters Delay time, SSP_CLK Clock (output) rising edge to Polarity = 0 MOSI (output) transition Delay time, SSP_CLK Clock (output) falling edge to Polarity = 1 MOSI (output) transition Doc ID 16482 Rev 2 SPEAr310 Min Max Unit -0.411 -0.342 ns -0.411 -0.342 ns 0.912 1.720 ns 0.912 1 ...
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... SPEAr310 Table 45. Switching characteristics over recommended operating conditions for SPI master mode (clock phase = 1 ) (continued) No. t d(ENL- 10 CLKH/L) td (CLKH/L- 11 ENH) Figure 41. SPI master mode external timing (clock phase = 1) SSP_CSn SSP_SCLK (Clock Polarity = 0) SSP_SCLK (Clock Polarity = 1) SSP_MISO SSP_MOSI 6.7 UART (Universal asynchronous receiver/transmitter) timing characteristics Figure 42 ...
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... UART Pulse Duration Transmit Data (TxD) UART Transmit Start Bit Parameters UART Pulse Duration Receive Data (RxD) UART Receive Start Bit Doc ID 16482 Rev 2 Min Max 3 0.99B B (1) (1) 0.99B B (1) (1) Min Max 0.97B 1.06B (1) (1) 0.97B 1.06B (1) (1) SPEAr310 Unit Mbps ns ns Units ns ns ...
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... SPEAr310 7 Package information In order to meet environmental requirements, ST offers these devices in different grades of ® ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ® ECOPACK trademark. Table 48. LFBGA289 ( 1.7 mm) mechanical data Dim 14.850 D1 E 14.850 ...
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... Package information Figure 43. LFBGA289 package dimensions Table 49. Thermal resistance characteristics Package LFBGA289 70/72 Θ (°C/W) JC 18.5 Doc ID 16482 Rev 2 SPEAr310 Θ (°C/W) JB 24.5 ...
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... Revision 1 Initial release. Changed “SPI” to “SSP” where applicable. Updated features list on coverpage. Updated Figure 1: Functional block diagram system architecture using SPEAr310 Corrected Figure 4: Typical SMII system Updated Section 3.3: Shared I/O pins – Added Section 3.3.1: PL_GPIO pin GPIOs and Section 3 ...
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... Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Philippines - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America 72/72 Please Read Carefully: © 2010 STMicroelectronics - All rights reserved STMicroelectronics group of companies www.st.com Doc ID 16482 Rev 2 SPEAr310 ...