WJLXT972ALC.A4-857341 Cortina Systems Inc, WJLXT972ALC.A4-857341 Datasheet - Page 23

• Manufacturer Part Number: WJLXT972ALC.A4-857341
• Description: TXRX ETH 10/100 SGL PORT 64-LQFP
• Manufacturer: Cortina Systems Inc

Specifications of WJLXT972ALC.A4-857341

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 1008-1042

LXT972A PHY
Datasheet
249186, Revision 5.2
13 September 2007
5.2.1.2
5.2.2
5.2.3
5.2.3.1
Cortina Systems
characteristics. On the receive side, the internal impedance is high enough that it has no
practical effect on the external termination circuit. (For the slew rate settings, see
Table 55, Transmit Control Register - Address 30, Hex 1E, on page
Remote Fault Detection and Reporting
The LXT972A PHY supports the remote fault detection and reporting mechanisms.
“Remote Fault” refers to a MAC-to-MAC communication function that is transparent to
PHY layer devices. It is used only during auto-negotiation, and is applicable only to
twisted-pair links.
Remote Fault Detection. register bit 4.13 in the Auto-Negotiation Advertisement Register
is reserved for Remote Fault indications. It is typically used when re-starting the auto-
negotiation sequence to indicate to the link partner that the link is down because the
advertising device detected a local fault.
When the LXT972A PHY receives a Remote Fault indication from its partner during auto-
negotiation, the following occurs:
MII Data Interface
The LXT972A PHY supports a standard Media Independent Interface (MII). The MII
consists of a data interface and a management interface. The MII Data Interface passes
data between the LXT972A PHY and a Media Access Controller (MAC). Separate parallel
buses are provided for transmit and receive. This interface operates at either 10 Mbps or
100 Mbps. The speed is set automatically, once the operating conditions of the network
link have been determined. For details, see
Increased MII Drive Strength. A higher Media Independent Interface (MII) drive strength
may be desired in some designs to drive signals over longer PCB trace lengths, or over
high-capacitive loads, through multiple vias, or through a connector. The MII drive
strength in the LXT972A PHY can be increased by setting register bit 26.11 through
software control. Setting register bit 26.11 = 1 through the MDC/MDIO interface sets the
MII pins (RXD[3:0], RX_DV, RX_CLK, RX_ER, COL, CRS, and TX_CLK) to a higher drive
strength.
Configuration Management Interface
The LXT972A PHY provides both an MDIO interface and a reduced hardware control
interface for device configuration and management.
MDIO Management Interface
MDIO management interface topics include the following:
The LXT972A PHY supports the IEEE 802.3 MII Management Interface also known as the
Management Data Input/Output (MDIO) Interface. This interface allows upper-layer
devices to monitor and control the state of the LXT972A PHY. The MDIO interface
consists of a physical connection, a specific protocol that runs across the connection, and
an internal set of addressable registers.
®
• register bit 5.13 in the Link Partner Base Page Ability Register is set.
• Remote Fault register bit 1.4 in the MII Status Register is set to pass this information
•
•
LXT972A Single-Port 10/100 Mbps PHY Transceiver
to the local controller.
Section 5.2.3.1.1, MDIO Addressing
Section 5.2.3.1.2, MDIO Frame Structure
Section 5.6, MII Operation, on page
5.2 Network Media / Protocol
78.)
30.
Support
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