WJLXT972ALC.A4-857341 Cortina Systems Inc, WJLXT972ALC.A4-857341 Datasheet - Page 5

• Manufacturer Part Number: WJLXT972ALC.A4-857341
• Description: TXRX ETH 10/100 SGL PORT 64-LQFP
• Manufacturer: Cortina Systems Inc

Specifications of WJLXT972ALC.A4-857341

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 1008-1042

LXT972A PHY
Datasheet
249186, Revision 5.2
13 September 2007
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Cortina Systems
Block Diagram ............................................................................................................................... 11
64-Pin LQFP Package: Pin Assignments ...................................................................................... 12
Management Interface Read Frame Structure ............................................................................. 24
Management Interface Write Frame Structure ............................................................................. 24
MII Interrupt Logic ......................................................................................................................... 25
Clocking for 10BASE-T ................................................................................................................. 31
Clocking for 100BASE-X .............................................................................................................. 32
Clocking for Link Down Clock Transition ......................................................................................32
Loopback Paths ............................................................................................................................ 34
100BASE-X Frame Format ...........................................................................................................35
100BASE-TX Data Path ............................................................................................................... 36
100BASE-TX Reception with No Errors ....................................................................................... 36
100BASE-TX Reception with Invalid Symbol ............................................................................... 37
100BASE-TX Transmission with No Errors .................................................................................. 37
100BASE-TX Transmission with Collision .................................................................................... 37
Protocol Sublayers ....................................................................................................................... 38
LED Pulse Stretching ................................................................................................................... 45
Typical Twisted-Pair Interface - Switch ......................................................................................... 48
Typical Twisted-Pair Interface - NIC ..............................................................................................49
Typical Media Independent Interface ............................................................................................ 50
100BASE-TX Receive Timing ....................................................................................................... 55
100BASE-TX Transmit Timing ...................................................................................................... 56
10BASE-T Transmit Timing .......................................................................................................... 57
10BASE-T Jabber and Unjabber Timing ......................................................................................58
10BASE-T SQE (Heartbeat) Timing ............................................................................................. 58
Auto-Negotiation and Fast Link Pulse Timing ............................................................................... 59
Fast Link Pulse Timing .................................................................................................................. 59
MDIO Input Timing ........................................................................................................................ 60
MDIO Output Timing...................................................................................................................... 60
Power-Up Timing ........................................................................................................................... 61
RESET_L Pulse Width and Recovery Timing ............................................................................... 61
PHY Identifier Bit Mapping ...........................................................................................................66
LQFP Package Specifications ....................................................................................................... 79
Link Establishment Overview ....................................................................................................... 29
®
LXT972A Single-Port 10/100 Mbps PHY Transceiver
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