WJLXT972ALC.A4-857341 Cortina Systems Inc, WJLXT972ALC.A4-857341 Datasheet - Page 31

• Manufacturer Part Number: WJLXT972ALC.A4-857341
• Description: TXRX ETH 10/100 SGL PORT 64-LQFP
• Manufacturer: Cortina Systems Inc

Specifications of WJLXT972ALC.A4-857341

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 1008-1042

LXT972A PHY
Datasheet
249186, Revision 5.2
13 September 2007
5.6.1
Note:
Figure 7
Cortina Systems
The following signals are used to transmit data from the MAC:
The LXT972A PHY supplies both clock signals as well as separate outputs for carrier
sense and collision. Data transmission across the MII is normally implemented in 4-bit-
wide nibbles.
MII Clocks
The LXT972A PHY is the master clock source for data transmission, and it supplies both
MII clocks (RX_CLK and TX_CLK). It automatically sets the clock speeds to match link
conditions.
Figure 7
The transmit data and control signals must always be synchronized to TX_CLK by the
MAC. The LXT972A PHY samples these signals on the rising edge of TX_CLK.
Clocking for 10BASE-T
®
TX_CLK
RX_CLK
XI
• CRS
• RX_CLK
• RX_DV
• RX_ER
• RXD[3:0]
• TX_CLK
• TX_EN
• TX_ER
• TXD[3:0]
• When the link is operating at 100 Mbps, the clocks are set to 25 MHz.
• When the link is operating at 10 Mbps, the clocks are set to 2.5 MHz.
LXT972A Single-Port 10/100 Mbps PHY Transceiver
through
Figure 9
show the clock cycles for each mode.
2.5 MHz during auto-negotiation and 10BASE-T Data & Idle
2.5 MHz during auto-negotiation and 10BASE-T Data & Idle
Constant 25 MHz
5.6 MII Operation
B3390-01
Page 31