LS027B7DH01 Sharp Microelectronics, LS027B7DH01 Datasheet - Page 18

• Manufacturer Part Number: LS027B7DH01
• Description: LCD Graphic Display Modules & Accessories 2.7 WQVGA HR-TFT 400x240 w/FPC
• Manufacturer: Sharp Microelectronics

Specifications of LS027B7DH01

• Pixel Density: 400 x 240
• Module Size (w X H X T): 62.8 mm x 42.82 mm
• Viewing Area (w X H): 58.8 mm x 35.28 mm
• Operating Temperature Range: - 20 C to + 70 C
• Attached Touch Screen: No
• Product: 2.7 in WQVGA Monochrome
• Display Mode: Transmissive
• Interface: Serial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

6-5) Input Signal Timing Chart
6-5-1 Data update mode (1 line)
SCS
SI
SCLK
Updates data of only one specified line. (M0=”H”、M2＝”L”)
tsSCS
tsSI
M0 M1 M2 DMYDMYDMYDMYDMYAG0 AG1 AG2 AG3 AG4 AG5 AG6 AG7 D1 D2 D3 D4
M0: Mode flag. Set for “H”. Data update mode (Memory internal data update)
M1: Frame inversion flag.
M2: All clear flag.
DUMMY DATA: Dummy data. It can be “H” or “L” (“L” is recommended.)
* For gate line address setting, refer to 6-6) Input Signal and Display.
* M1: Frame inversion fl is enaled when EXTMODE=”L”.
* When SCS becomes “L”, M0 and M2 are cleared.
thSI
Mode select period
(3ck+5ckDMY)
twSCLKL
When “L”, display mode (maintain memory internal data).
When “H”, outputs VCOM=”H”, and when “L”, outputs VCOM=”L”.
When EXTMODE=”H”, it can be “H” or “L”.
twSCLKH
Refer to 6-5-4) All Clear Mode to execute clear.
※ Data write period
Data is being stored in 1
※ Data transfer period
Data written in 1
twSCSH
Gate line address select period
(8ck)
st
Date write period
latch is being transferred (written) to pixel internal memory circuit.
(400ck)
st
SPEC No.
D397 D398 D399 D400
latch block of binary driver on panel.
LCY-1210401A
Date transfer period
MODEL No.
DUMMY DATA(don't care)
(16ck)
LS027B7DH01
thSCS
PAGE
twSCSL
15