LFXP2-5E-B-EVN Lattice, LFXP2-5E-B-EVN Datasheet - Page 17

• Manufacturer Part Number: LFXP2-5E-B-EVN
• Description: MCU, MPU & DSP Development Tools LatticeXP2 Brevia Dev kit
• Manufacturer: Lattice
• Series: -r
• Type: FPGAr

Specifications of LFXP2-5E-B-EVN

• Processor To Be Evaluated: LFXP2-5E-6TN144C
• Data Bus Width: 8 bit
• Interface Type: RS-232, JTAG, SPI
• Operating Supply Voltage: 3.3 V
• Silicon Manufacturer: Lattice Semiconductor
• Silicon Family Name: LatticeXP2
• Kit Contents: Evaluation Board, USB Cables, AC Adapter, Quick Start Guide
• Features: Serial RS232 Interface, JTAG Interface
• Svhc: No
• Rohs Compliant: Yes
• Contents: Board, Cables, Documentation, Power Supply
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: LFXP2-5E-6TN144C

Lattice Semiconductor
Table 9. JTAG Programming Interface
FPGA
The Lattice XP2 Brevia board is based on the Lattice Semiconductor LatticeXP2 non-volatile FPGA. The board is
populated with a 5K LUT device in a 144 TQFP package. A complete description of the device can be found in the
LatticeXP2 Family Data Sheet
JTAG Cable Color Coding
Table 10. JTAG Cable Color Coding
Software Requirements
You should install the following software before you begin developing designs for the evaluation board:
• ispLEVER Starter or ispLEVER 7.2 SP2 or later
• ispVM System 17.3.3
Mechanical Specifications
Dimensions: 3-1/4 in. [L] x 2 in. [W] x 3/4 in. [H]
Environmental Requirements
The evaluation board must be stored between -40° C and 100° C. The recommended operating temperature is
between 0° C and 55° C.
JTAG Connector J3
JTAG Connector
Pin Number
10
1
2
3
4
5
6
7
8
9
JTAG Connector
JTAG_TDO
JTAG_TMS
JTAG_TCK
Pin Name
JTAG_TDI
and on the
GND
GND
GND
GND
GND
3.3V
Orange
Yellow
Brown
Green
Color
Violet
Black
Blue
Red
-
-
LatticeXP2 web
J3 Pin Number
Pin Number
FPGA
17
82
80
79
81
10
—
—
—
—
—
—
1
2
3
4
5
6
7
8
9
page.
LatticeXP2 Brevia Development Kit
Association
JTAG_TDO
JTAG_TMS
JTAG_TCK
GND
GND
GND
GND
GND
Pin Name
JTAG_TDI
TDO
VCC
TMS
TCK
TDI
FPGA
—
—
—
—
—
—
Pin Functionality
User’s Guide
GND
GND
GND
GND
GND
TDO
VCC
TMS
TCK
TDI