LFXP2-5E-B-EVN Lattice, LFXP2-5E-B-EVN Datasheet - Page 18

• Manufacturer Part Number: LFXP2-5E-B-EVN
• Description: MCU, MPU & DSP Development Tools LatticeXP2 Brevia Dev kit
• Manufacturer: Lattice
• Series: -r
• Type: FPGAr

Specifications of LFXP2-5E-B-EVN

• Processor To Be Evaluated: LFXP2-5E-6TN144C
• Data Bus Width: 8 bit
• Interface Type: RS-232, JTAG, SPI
• Operating Supply Voltage: 3.3 V
• Silicon Manufacturer: Lattice Semiconductor
• Silicon Family Name: LatticeXP2
• Kit Contents: Evaluation Board, USB Cables, AC Adapter, Quick Start Guide
• Features: Serial RS232 Interface, JTAG Interface
• Svhc: No
• Rohs Compliant: Yes
• Contents: Board, Cables, Documentation, Power Supply
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: LFXP2-5E-6TN144C

LatticeXP2 Brevia Development Kit
Lattice Semiconductor
User’s Guide
The evaluation board can be damaged without proper anti-static handling.
Glossary
DIP: Dual In-line Package
FPGA: Field-Programmable Gate Array
LED: Light Emitting Diode
LUT: Look-Up Table
PCB: Printed Circuit Board
RoHS: Restriction of Hazardous Substances Directive
PLL: Phase Locked Loop
SPI: Serial Peripheral Interface
SRAM: Static Random Access Memory
UART: Universal Asynchronous Receiver/Transmitter
WDT: Watchdog Timer
Troubleshooting
The LatticeXP2 Brevia Evaluation Board is not responsive.
• Verify the DC power supply is providing 6V DC.
• Remove any jumper on J5.
• Verify the LatticeXP2 is programmed.
The functionality displayed by the board does not match the demo features described.
It is possible the LatticeXP2 Brevia Evaluation Board has been reprogrammed. You can either reprogram the FPGA
with the demonstration bitstream, or read the checksum of the bitstream loaded in the FPGA. To restore the
LatticeXP2 Brevia Evaluation Board to the factory default, see the Download Demo Designs section of this docu-
ment for details on downloading and reprogramming the device.
You can use ispVM System to read the checksum of the bitstream programmed into the FPGA. This value can be
compared against the checksum stored in the JEDEC file. The JEDEC file checksum value is the last line in the file.
This may allow you to determine the contents of the FPGA.
A final option is to use ispVM System to read the current bitstream in the FPGA, and then to reprogram the FPGA
with your desired bitstream.
Ordering Information
China RoHS Environment-Friendly
Description
Ordering Part Number
Use Period (EFUP)
LatticeXP2 Brevia Development Kit
LFXP2-5E-B-EVN
18