CS8427-CZZ Cirrus Logic Inc, CS8427-CZZ Datasheet - Page 30

• Manufacturer Part Number: CS8427-CZZ
• Description: Audio DSPs 96 kHz Digital Audio Transceiver
• Manufacturer: Cirrus Logic Inc

Specifications of CS8427-CZZ

• Operating Supply Voltage: 4.5 V to 5.5 V
• Supply Current: 6.3 mA to 76.6 mA
• Operating Temperature Range: - 10 C to + 70 C
• Mounting Style: SMD/SMT
• Input Voltage: 4.8 V to 5.8 V
• Package / Case: TSSOP-28
• Rohs Compliant: Yes
• Supply Voltage Range: 4.5V To 5.5V
• Logic Case Style: TSSOP
• No. Of Pins: 28
• Supply Voltage Max: 5.5V
• Supply Voltage Min: 4.5V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

SPD1:SPD0 - Serial Audio Output Port Data Source
11.4 Clock Source Control (04h)
This register configures the clock sources of various blocks. In conjunction with the Data Flow Control register, var-
ious Receiver/Transmitter/Transceiver modes may be selected.
RUN - Controls the internal clocks, allowing the CS8427 to be placed in a “powered down”, low current consumption,
CLK1:0 - Output side master clock input (OMCK) frequency to output sample rate (Fso) ratio selector. If these bits
OUTC - Output Time Base
INC - Input Time Base Clock Source
RXD1:0 - Recovered Input Clock Source
30
state.
are changed during normal operation, then always stop the CS8427 first (RUN = 0), write the new value, then start
the CS8427 (RUN = 1).
7
0
Default = ‘10’
00 - Reserved
01 - Serial Audio Input Port
10 - AES3 receiver
11 - Reserved
Default = ‘0’
0 - Internal clocks are stopped. Internal state machines are reset. The fully static
1 - Normal part operation. This bit must be written to the 1 state to allow the CS8427
Default = ‘00’
00 - OMCK frequency is 256 * Fso
01 - OMCK frequency is 384 * Fso
10 - OMCK frequency is 512 * Fso
11 - Reserved
Default = ‘0’
0 - OMCK input pin, modified by the selected divide ratio bits CLK1:0.
1 - Recovered Input Clock
Default = ‘0’
0 - Recovered Input Clock
1 - OMCK input pin, modified by the selected divide ratio bits CLK1:0.
Default = ‘00’
00 - 256 * Fsi, where Fsi is derived from the ILRCK pin (only possible when the
01 - 256 * Fsi, where Fsi is derived from the AES3 input frame rate
10 - Bypass the PLL and apply an external 256 * Fsi clock through the RMCK pin. The AES3
11 - Reserved.
control port is operational, allowing registers to be read or changed. Reading and
writing the U and C data buffers is not possible. Power consumption is low.
to begin operation. All input clocks should be stable in frequency and phase when
RUN is set to 1.
serial audio input port is in slave mode)
receiver is held in synchronous reset. This setting is useful to prevent UNLOCK
interrupts when using an external RMCK and inputting data through the serial audio input port.
RUN
6
CLK1
5
CLK0
4
OUTC
3
INC
2
RXD1
1
CS8427
DS477F5
RXD0
0