CS8427-CZZ Cirrus Logic Inc, CS8427-CZZ Datasheet - Page 54

• Manufacturer Part Number: CS8427-CZZ
• Description: Audio DSPs 96 kHz Digital Audio Transceiver
• Manufacturer: Cirrus Logic Inc

Specifications of CS8427-CZZ

• Operating Supply Voltage: 4.5 V to 5.5 V
• Supply Current: 6.3 mA to 76.6 mA
• Operating Temperature Range: - 10 C to + 70 C
• Mounting Style: SMD/SMT
• Input Voltage: 4.8 V to 5.8 V
• Package / Case: TSSOP-28
• Rohs Compliant: Yes
• Supply Voltage Range: 4.5V To 5.5V
• Logic Case Style: TSSOP
• No. Of Pins: 28
• Supply Voltage Max: 5.5V
• Supply Voltage Min: 4.5V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

When reading data in one byte mode, a single byte
is returned, which can be from channel A or B data,
depending on a register control bit. If a write is be-
ing done, the CS8427 expects a single byte to be
input to its control port. This byte will be written to
both the A and B locations in the addressed word.
One byte mode saves the user substantial control
port access time, as it effectively accesses 2 bytes
worth of information in 1 byte's worth of access
time. If the control port's autoincrement addressing
is used in combination with this mode, multi-byte
accesses such as full-block reads or writes can be
done especially efficiently.
Two Byte mode
There are those applications in which the A and B
channel status blocks will not be the same, and the
user is interested in accessing both blocks. In
these situations, two byte mode should be used to
access the E buffer.
In this mode, a read will cause the CS8427 to out-
put two bytes from its control port. The first byte out
will represent the A channel status data, and the
2nd byte will represent the B channel status data.
Writing is similar, in that two bytes must now be in-
put to the CS8427's control port. The A channel
status data is first, B channel status data second.
19.2
The CS8427 U bit manager has two operating
modes: transmit all zeros and block mode.
54
AES3 User (U) Bit Management
19.2.1 Mode 1: Transmit All Zeros
Mode 1 causes only zeros to be transmitted in the
output U data, regardless of E buffer contents or
U data embedded in an input AES3 data stream.
This mode is intended for the user who does not
want to transceive U data, and simply wants the
output U channel to contain no data.
19.2.2 Mode 2: Block Mode
Mode 2 is very similar to the scheme used to con-
trol the C bits. Entire blocks of U data are buffered
from input to output, using a cascade of 3 block-
sized RAMs to perform the buffering. The user has
access to the second of these 3 buffers, denoted
the E buffer, through the control port. Block mode
is designed for use in AES3 in, AES3 out situations
in which input U data is decoded using a microcon-
troller through the control port. It is also the only
mode in which the user can merge his own U data
into the transmitted AES3 data stream.
The U buffer access only operates in two byte
mode, since there is no concept of A and B blocks
for user data. The arrangement of the data is as fol-
lows:Bit15[A7]Bit14[B7]Bit13[A6]Bit12[B6]...Bit1[A
0]Bit0[B0]. The arrangement of the data in the
each byte is that the MSB is the first received bit
and is the first transmitted bit. The first byte read is
the first byte received, and the first byte sent is the
first byte transmitted. If you read two bytes from the
E buffer, you will get the following arrangement:
A[7]B[7]A[6]B[6]....A[0]B[0].
CS8427
DS477F5