XRT75R12IB-F Exar Corporation, XRT75R12IB-F Datasheet - Page 4

• Manufacturer Part Number: XRT75R12IB-F
• Description: Peripheral Drivers & Components (PCIs) 12 Channel 3.3V-5V temp -45 to 85C
• Manufacturer: Exar Corporation

Specifications of XRT75R12IB-F

• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3.3 V
• Package / Case: TBGA-420
• Ic Interface Type: Parallel, Serial
• Supply Voltage Range: 3.135V To 3.465V
• Operating Temperature Range: -40°C To +85°C
• Digital Ic Case Style: BGA
• No. Of Pins: 420
• Filter Terminals: SMD
• Rohs Compliant: Yes
• Data Rate Max: 51.84Mbps
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

XRT75R12
TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
5.0 JITTER ..................................................................................................................................................37
6.0 DIAGNOSTIC FEATURES ...................................................................................................................41
7.0 MICROPROCESSOR INTERFACE BLOCK ........................................................................................45
F
F
F
F
F
T
F
T
T
F
T
T
F
F
F
F
T
T
T
F
F
F
F
F
F
T
F
T
F
T
F
T
T
T
T
T
IGURE
IGURE
IGURE
IGURE
IGURE
ABLE
IGURE
ABLE
ABLE
IGURE
ABLE
ABLE
IGURE
IGURE
IGURE
IGURE
ABLE
ABLE
ABLE
IGURE
IGURE
IGURE
IGURE
IGURE
IGURE
ABLE
IGURE
ABLE
IGURE
ABLE
IGURE
ABLE
ABLE
ABLE
ABLE
ABLE
4.3 B3ZS/HDB3 ENCODER .................................................................................................................................. 29
4.4 TRANSMIT PULSE SHAPER ......................................................................................................................... 30
4.5 E3 LINE SIDE PARAMETERS ........................................................................................................................ 31
4.6 TRANSMIT DRIVE MONITOR ........................................................................................................................ 36
4.7 TRANSMITTER SECTION ON/OFF ............................................................................................................... 36
5.1 JITTER TOLERANCE ..................................................................................................................................... 37
5.2 JITTER TRANSFER ........................................................................................................................................ 39
5.3 JITTER ATTENUATOR ................................................................................................................................... 39
6.1 PRBS GENERATOR AND DETECTOR ......................................................................................................... 41
6.2 LOOPBACKS .................................................................................................................................................. 42
6.3 TRANSMIT ALL ONES (TAOS) ...................................................................................................................... 44
7.1 THE MICROPROCESSOR INTERFACE BLOCK SIGNALS ......................................................................... 45
7.2 ASYNCHRONOUS AND SYNCHRONOUS DESCRIPTION .......................................................................... 46
7.3 REGISTER MAP ............................................................................................................................................. 48
THE GLOBAL/CHIP-LEVEL REGISTERS ................................................................................................................ 57
REGISTER DESCRIPTION - GLOBAL REGISTERS ............................................................................................... 58
5: E3 T
6: STS-1 P
7: STS-1 T
8: DS3 P
9: DS3 T
10: J
11: J
12: J
13: S
14: XRT75R12 M
15: A
16: S
17: C
18: L
19: APS/R
20: APS/R
4.3.1 B3ZS ENCODING ....................................................................................................................................................... 29
4.3.2 HDB3 ENCODING ....................................................................................................................................................... 29
4.4.1 GUIDELINES FOR USING TRANSMIT BUILD OUT CIRCUIT .................................................................................. 30
5.1.1 DS3/STS-1 JITTER TOLERANCE REQUIREMENTS ................................................................................................ 37
5.1.2 E3 JITTER TOLERANCE REQUIREMENTS .............................................................................................................. 38
5.3.1 JITTER GENERATION................................................................................................................................................ 40
6.2.1 ANALOG LOOPBACK ................................................................................................................................................ 42
6.2.2 DIGITAL LOOPBACK ................................................................................................................................................. 43
6.2.3 REMOTE LOOPBACK ................................................................................................................................................ 43
18. B3ZS E
17. D
19. HDB3 E
20. T
21. P
22. B
23. T
24. T
25. J
26. I
27. I
28. J
29. PRBS MODE ................................................................................................................................................................... 41
30. A
31. D
32. R
33. T
34. S
35. A
36. S
ITTER
ITTER
ITTER
IST AND
ELECTING THE
SYNCHRONOUS
YNCHRONOUS
OMMAND
ITTER
ITTER
NPUT
NPUT
RANSMIT
ULSE
ELLCORE
RANSMIT
RANSMIT
NALOG
RANSMIT
IMPLIFIED
SYNCHRONOUS
YNCHRONOUS
UAL
IGITAL
EMOTE
RANSMITTER LINE SIDE OUTPUT AND RECEIVER LINE SIDE INPUT SPECIFICATIONS
RANSMITTER
ULSE
-R
EDUNDANCY
EDUNDANCY
A
T
T
RANSMITTER
ULSE
M
J
J
T
T
RANSFER
RANSFER
MPLITUDE VERSUS
AIL
NCODING
ITTER
ITTER
NCODING
L
A
OLERANCE
RANSFER
L
L
ASK FOR
OOPBACK
R
M
DDRESS
OOPBACK
OOPBACK
P
O
D
A
GR-253 CORE T
D
B
EGISTER
ASK
ULSE
M
LL
RIVER
UPUT
ATA
LOCK
ICROPROCESSOR
ASK
T
T
T
O
M
OLERANCE
OLERANCE FOR
µP I
T
IMING
E
NES
ICROPROCESSOR
L
S
P
µP I
F
IMING
F
S
QUATIONS
F
E3 (34.368
P
R
E
INE
L
T
R
M
ORMAT
PECIFICATION
ASS
D
ORMAT
HAPE
L
............................................................................................................................................................ 43
ORMAT
ULSE
M
OCATIONS OF
QUATIONS
........................................................................................................................................................... 42
........................................................................................................................................................... 43
RANSMIT
EQUIREMENTS AND
NTERFACE
ECIEVE
INE
IAGRAM OF THE
A
ONITOR SET
(TAOS) ............................................................................................................................................ 44
NTERFACE
EASUREMENTS
DDRESS
S
S
M
S
IDE
PECIFICATIONS
S
PECIFICATIONS
T
ASKS
T
IDE
(
M
................................................................................................................................................. 29
................................................................................................................................................. 30
EST
EMPLATE FOR
F
ENCODER AND DECODER ARE DISABLED
O
C
............................................................................................................................................... 35
OR
ODULATION
RANSMIT
C
UTPUT AND
ONTROL
O
MBITS
........................................................................................................................................... 33
........................................................................................................................................... 40
I
M
C
S
ONTROL
NTERFACE
E3..................................................................................................................................... 38
UTPUT AND
DS3/STS-1 ...................................................................................................................... 38
/R
S
-
IRCUIT
IGNALS
AP
UP
G
IGNALS
EFERENCES
I
NTERFACE
,
LOBAL
................................................................................................................................... 36
/
.................................................................................................................................. 37
M
WITHIN THE
S
)
O
R
ICROPROCESSOR
............................................................................................................................... 48
.............................................................................................................................. 30
J
INTERFACE AS PER ITU
R
............................................................................................................................. 47
EGISTER
UTPUT
F
D
ITTER
DS3
R
EGISTER
D
REQUENCY
URING
S
R
ECEIVER
URING
R
IGNALS
EGISTERS
ECEIVER
M
AS PER
................................................................................................................... 39
A
P
ODE
TTENUATOR
XRT75R12.............................................................................................. 48
ULSE
P
- CR8 (A
P
ROGRAMMED
- CR0 (A
............................................................................................................ 45
ROGRAMMED
L
.......................................................................................................... 45
(J
INE
........................................................................................................ 57
T
L
B
ITTER
II
INE
EMPLATE FOR
ELLCORE
I
NTERFACE
S
DDRESS
IDE
S
DDRESS
P
IDE
T
-
ERFORMANCE
I
OLERANCE
T
NPUT
I/O R
G.703 ............................................................................. 31
I
I/O R
GR-499 ......................................................................... 34
NPUT
).................................................................................... 29
L
B
L
OCATION
S
LOCK
EAD AND
OCATION
SONET STS-1 A
EAD AND
PECIFICATIONS
S
PECIFICATIONS
) ......................................................................... 39
........................................................................ 45
...................................................................... 40
= 0
W
= 0
W
RITE
X
.............................................................. 32
RITE
X
08) ....................................................... 58
00) ..................................................... 58
(GR-499) ........................................ 35
O
O
PERATIONS
PPLICATIONS
(GR-253)..................................... 34
PERATIONS
.................................... 48
.................................. 47
................................. 33
REV. 1.0.4