XRT75R12IB-F Exar Corporation, XRT75R12IB-F Datasheet - Page 84

• Manufacturer Part Number: XRT75R12IB-F
• Description: Peripheral Drivers & Components (PCIs) 12 Channel 3.3V-5V temp -45 to 85C
• Manufacturer: Exar Corporation

Specifications of XRT75R12IB-F

• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3.3 V
• Package / Case: TBGA-420
• Ic Interface Type: Parallel, Serial
• Supply Voltage Range: 3.135V To 3.465V
• Operating Temperature Range: -40°C To +85°C
• Digital Ic Case Style: BGA
• No. Of Pins: 420
• Filter Terminals: SMD
• Rohs Compliant: Yes
• Data Rate Max: 51.84Mbps
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

L
A
XRT75R12
TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
OCATION
DDRESS
0xC-
0xD-
0
0
0xA-
0xB-
0xE-
0xF-
0x0-
0x2-
0x3-
0x4-
0x5-
0x6-
0x7-
0x8-
X
X
B
1-
9-
IT
B
Msb
R/W
IT
N
UMBER
1
0
7
T
T
APST
APST
ABLE
CIE
CIE
ABLE
T
0
ABLE
43: XRT75R12 R
42: J
IER10
JA in Tx Path Ch_n
IER11
IER0
IER1
IER2
IER3
IER4
IER5
IER6
IER7
IER8
IER9
CIS
CIS
44: E
1
B
R/W
IT
JA0 Ch_n
ITTER
6
N
RROR
AME
ISR10
ISR11
ISR0
ISR1
ISR2
ISR3
ISR4
ISR5
ISR6
ISR7
ISR8
ISR9
2
A
TTENUATOR
C
OUNTER
B
R/W
EGISTER
AS10
AS11
AS0
AS1
AS2
AS3
AS4
AS5
AS6
AS7
AS8
AS9
IT
3
5
T
R/W
R/W
YPE
MSB
C
TC10
TC11
MAP
TC0
TC1
TC2
TC3
TC4
TC5
TC6
TC7
TC8
TC9
ONTROL
(n = [0:11] &
4
Jitter Attenuator in Transmit/Receive Path Select Bit:
This input pin is used to configure the Jitter Attenuator (within
Channel_n) to operate in either the Transmit or Receive path, as
described below.
0 - Configures the Jitter Attenuator (within Channel_n) to operate in the
Receive Path.
1 - Configures the Jitter Attenuator (within Channel_n) to operate in the
Transmit Path.
Jitter Attenuator Configuration Select Input - Bit 0:
See the description for Bit 2 (JA1 Ch_n).
YTE
B
R/W
SHOWING
IT
R
RC10
RC11
4
RC0
RC1
RC2
RC3
RC4
RC5
RC6
RC7
RC8
RC9
EGISTER
R
5
EGISTER
81
M
= 0-5 & 8-D)
E
CC10
CC11
CC0
CC1
CC2
CC3
CC4
CC5
CC6
CC7
CC8
CC9
RROR
- C
6
B
R/W
- C
IT
HANNEL N
3
HANNEL
C
JA10
JA11
JA0
JA1
JA2
JA3
JA4
JA5
JA6
JA7
JA8
JA9
OUNTER
7
D
ESCRIPTION
APSR
APSR
A
n A
8
DDRESS
B
MSB
R/W
IT
DDRESS
2
9
YTE
EM10
EM11
EM0
EM1
EM2
EM3
EM4
EM5
EM6
EM7
EM8
EM9
L
A
OCATION
R
L
EGISTERS
OCATION
B
R/W
EL10
EL11
IT
EL0
EL1
EL2
EL3
EL4
EL5
EL6
EL7
EL8
EL9
B
1
= 0
= 0
(EM_
XM
EH10
EH11
XM
EH0
EH1
EH2
EH3
EH4
EH5
EH6
EH7
EH8
EH9
A
C
N
7
REV. 1.0.4
9th bit
)
B
R/W
IT
D E F
0
PN VN