MPC8536BVTAUL Freescale Semiconductor, MPC8536BVTAUL Datasheet

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... Three-speed support (10/100/1000 Mbps) – Two IEEE Std 802.3®, IEEE 802.3u, IEEE 802.3x, IEEE 802.3z, IEEE 802.3ac, IEEE 802.3ab, and IEEE Std 1588™-compatible controllers © 2010 Freescale Semiconductor, Inc. All rights reserved. Document Number: MPC8535EEC MAPBGA–783 – ...

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... Part Numbers Fully Addressed by This Document . . 121 4.2 Part Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 4.3 Part Numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 5 Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 5.1 Package Parameters for the MPC8535E FC-PBGA . 123 5.2 Mechanical Dimensions of the MPC8535E FC-PBGA124 6 Product Documentation 125 7 Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . 125 Block Power Supply Decoupling Freescale Semiconductor ...

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... PowerQUICC III software The UART_SOUT[0:1] and TEST_SEL pins must be set to a proper state during POR configuration. Please refer to MPC8535E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 3 Freescale Semiconductor e500 Core 512-Kbyte 32-Kbyte ...

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... NC SGND SRDS [5] [7] EN SD1_ SD1_ AVDD_ SD1_RX SD1_RX SV DD PLL_ SGND SGND IMP_CAL TDO SRDS [5] [7] TPD _TX Freescale Semiconductor AG AH USB1_ USB1_ 1 STP DIR USB1_ PWR- FAULT USB3_D USB3_D 3 [1] [0] USB3_D USB3_D 4 [3] [2] USB3_D USB3_ 5 [4] CLK USB3_D USB3_D 6 [6] ...

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... MA MA MECC 12 GND [11] [9] [7] MBA MECC MDQS MAPAR_ 13 [2] [6] [8] ERR MDQ MECC GND [27] [1] MPC8535E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 3 Freescale Semiconductor MDQ MDQ MDQ MDQ GND [46] [47] [34] [56] MDQ MDQ MDQ MDQ GV DD [42] [43] [35] [60] MDQ MDQ ...

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... OV DD CD/GPIO CTS DAT GPIO[15] [0] [3] [4] UART_ UART_ SDHC_ SDHC_ GND SIN RTS DAT DAT [1] [1] [0] [1] IRQ[10]/ IRQ[9]/ PCI1_ SDHC_ SDHC_ DMA_ DMA_ DAT REQ CLK DREQ[3] DACK[3] [2] [2] IRQ[11]/ PCI1_ IIC2_ DMA_ OV DD SYSCLK GNT SDA DDONE[3] [2] Freescale Semiconductor ...

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... LDP LSYNC_ 27 GND GND [2] IN AVDD_ LSYNC_ 28 MVREF GND LBIU OUT MPC8535E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 3 Freescale Semiconductor DETAIL C MDIC GV DD GND GND GND [0] LCS5/ LCS6/ MDQ LCS DMA_ DMA_ GND [18] [4] DREQ2 DACK2 MDQS MDQ LA LA ...

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... PCI1_ PCI1_ PCI1_ GND AD AD GND AD [14] [15] [11] PCI1_ PCI1_ PCI1_ PCI1_ [7] [9] [10] [12] PCI1_ PCI1_ PCI1_ PCI1_ C_BE [1] [4] [8] [0] PCI1_ PCI1_ PCI1_ PCI1_ GND CLK [0] [2] [3] PCI1_ POWER_ TMS AD EN [6] SD1_ SGND IMP_CAL TDO TCK TDI _TX Freescale Semiconductor ...

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... Request PCI1_REQ[0] Request PCI1_GNT[4:3]/GPIO[3:2] Grant PCI1_GNT[2:1] Grant PCI1_GNT[0] Grant PCI1_CLK PCI Clock MPC8535E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 3 Freescale Semiconductor Table 1. MPC8535E Pinout Listing Signal Name Package Pin Number PCI AB15,Y17,AA17,AC15, AB17,AC16,AA18, AD17,AE17,AB18, AB19,AE18,AC19, AF18,AE19,AC20, AF23,AE23,AC23, AH24,AH23,AG24, AE24,AG25,AD24, ...

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... A11,F9,E9,B12,A5, A12,D11,F7,E10,F10 A4,B5,B13 D3,H6,C4,G6 H10,K10,G10,H9 A9,J11,J6,A8,J13,H8 B9,H11,K6,B8,H13,J8 E5,H7,E6,F6 H15,K15 Local Bus Controller Interface Power Pin Type Notes Supply I/O GV — DD I/O GV — — — — DD I/O GV — DD I/O GV — — — — — — — — — — Freescale Semiconductor ...

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... Amux LCLK[0:2] Local bus clock LSYNC_IN Synchronization LSYNC_OUT Local bus DLL DMA_DACK[0:1] DMA Acknowledge /GPIO[10:11] MPC8535E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 3 Freescale Semiconductor Table 1. MPC8535E Pinout Listing Signal Name Package Pin Number K22,L21,L22,K23,K24, L24,L25,K25,L28,L27, K28,K27,J28,H28,H27, G27,G26,F28,F26,F25, E28,E27,E26,F24,E24, C26,G24,E23,G23,F22, G22,G21 ...

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... AH7,AG6,AH6,AG5, AG4,AH4,AG3,AH3, AG7, AG8, AH9,AH5 Power Pin Type Notes Supply I OV — — DD I I/O OV — — — 5 — — — — DD I/O OV — — — 5 — — — — DD — — — — — 27 Freescale Semiconductor ...

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... Receive clock Three-Speed Ethernet Controller (Gigabit Ethernet 3) TSEC3_TXD[7:0] Transmit data TSEC3_TX_EN Transmit Enable TSEC3_TX_ER Transmit Error MPC8535E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 3 Freescale Semiconductor Table 1. MPC8535E Pinout Listing Signal Name Package Pin Number Programmable Interrupt Controller Y14 AB14 AG22,AF17,AB23, AF19,AG17,AF16, ...

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... AH10 AH11 AG12,AH12,AH13, AG11 AE8,AC10,AF9,AA10 AG13 AG10 eSPI AF8 AD9 AD8 AE8,AC10,AF9,AA10 DUART AE11,Y12 AB12,AD12 AC12,AF12 Power Pin Type Notes Supply I LV — — — — — — — 5,9,29 DD 5,9, 5,9, 5,9, — Freescale Semiconductor ...

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... Reserved SD2_PLL_TPD PLL test point Digital SD2_REF_CLK PLL Reference clock SD2_REF_CLK PLL Reference clock complement Reserved Reserved MPC8535E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 3 Freescale Semiconductor Table 1. MPC8535E Pinout Listing Signal Name Package Pin Number AF10,AA12 interface AG21 AH22 AH15 ...

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... W15 Clock AF15 AH14 AC13 JTAG Power Pin Type Notes Supply I/O OV — DD I/O OV — DD I/O OV — I/O OV — DD I/O OV — DD I/O OV — DD I/O OV — DD I/O OV — DD I/O OV — DD I/O OV — — — — 2 — 6 6,9, 6, — — Freescale Semiconductor ...

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... GMAC 3 I/O supply GVDD SSTL2 DDR supply BVDD Local bus I/O supply SVDD SerDes 1 core logic supply MPC8535E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 3 Freescale Semiconductor Table 1. MPC8535E Pinout Listing Signal Name Package Pin Number AG28 AH28 AF28 AH27 AH21 ...

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... XV — DD — S2V — DD — X2V — DD — V — DD_CORE — V — DD_PLAT — AV 20,28 DD_CORE — DD_PLAT — DD_DDR — DD_LBIU 20 — AV DD_PCI1 — DD_SRDS — DD_SRDS2 — DD_CORE — DD_PLAT — — — — — — Freescale Semiconductor ...

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... PLL test point analog SD2_IMP_CAL_RX Rx impedance calibration SD2_IMP_CAL_TX Tx impedance calibration SD2_PLL_TPA PLL test point analog Reserved Reserved NC MPC8535E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 3 Freescale Semiconductor Table 1. MPC8535E Pinout Listing Signal Name Package Pin Number M28,N26,P24,P27, R25,T28,U24,U26,V24, W25,Y28,AA24,AA26, AB24,AB27,AD28 R12,M10,N11,L12 P8,P9,N6,M8 V27 ...

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... MPC8535E PowerQUICC III Integrated Processor Hardware Specifications, Rev Table 1. MPC8535E Pinout Listing Signal Name Package Pin Number Ratio.” Section 22.3, “e500 Core PLL Ratio.” /V /GND planes internally and may be used by the core power supply to DD_CORE DD_PLAT . DD Power Pin Type Supply . DD Freescale Semiconductor Notes ...

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... This section covers the ratings, conditions, and other characteristics. 2.1.1 Absolute Maximum Ratings Table 2 provides the absolute maximum ratings. MPC8535E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 3 Freescale Semiconductor Table 1. MPC8535E Pinout Listing Signal Name Package Pin Number Overall DC Electrical Characteristics Power ...

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... –0.3 to ( –0.3 to ( –0.3 to ( –0.3 to (BV + 0.3) — –0.3 to ( –55 to 150 C Specifications,” for details on Figure 2. Table 2 are the recommended Freescale Semiconductor — — — — — — — — — 3 — 3 — 3 — ...

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... Caution: OVIN must not exceed OVDD by more than 0.3 V. This limit may be exceeded for a maximum during power-on reset and power-down sequences. 5. Caution: L/TV must not exceed L/TV IN power-on reset and power-down sequences. 6. Minimum temperature is specified with T MPC8535E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 3 Freescale Semiconductor Symbol V DD_CORE V AV (eTSEC1) (eTSEC3) ...

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... SYSCLK. CLOCK references MCLK. CLOCK references EC_GTX_CLK125. CLOCK references LCLK. CLOCK references PCI1_CLK or SYSCLK. CLOCK Table 2 for actual recommended core voltage). Voltage to the n signal (nominally set to GV REF 1 CLOCK /OV / and LV based receivers are simple appropriate for the DD Freescale Semiconductor Table 2. ...

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... During the Deep Sleep state, the VDD core supply is removed. But all other power supplies remain applied. Therefore, there is no requirement to apply the VDD core supply before any other power rails when the silicon waking from Deep Sleep. MPC8535E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 3 Freescale Semiconductor Table 4. Output Drive Capability Programmable Output Impedance (Ω ...

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... Freescale Semiconductor 9 Notes 1 ...

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... Mean power is provided for information purposes only and is the mean power consumed by a statistically significant range of devices. 8. Maximum operating junction temperature (see 9. Platform power is the power supplied to all the See Section 2.23.6.1, “SYSCLK to Platform Frequency supports. MPC8535E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 3 Freescale Semiconductor V Junction Platfor Tempera ...

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... Unit — 133 MHz — 1.0 2.1 ns — — +/-150 ps Section 2.23.3, “e500 Core PLL Ratio,” Typical Max Unit Notes — 66 MHz — 1.0 2.1 ns — and minimum clock CCB Freescale Semiconductor Notes 1 — 2 — for ratio — — 1 — ...

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... PLL-based devices to track DDRCLK drivers with the specified jitter. 4. For spread spectrum clocking, guidelines are +0% to –1% down spread at a modulation rate between 20 kHz and 60 kHz on DDRCLK. MPC8535E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 3 Freescale Semiconductor Symbol Min f — ...

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... Table 11. PLL Lock Times Min Max — 100 — 50 — 50 Min Max Unit Notes μs 100 — — 3 — Sysclk 1 μs 100 — — 4 — SYSCLKs 1 2 — SYSCLKs 1 — 5 SYSCLKs 1 — 1 SYSCLK — Unit Notes μs — μs — μs — Freescale Semiconductor ...

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... DRAM expected to be equal to 0.5 × REF Peak-to-peak noise may not exceed ±1% of the DC value. REF 3. Output leakage is measured with all outputs disabled MPC8535E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 3 Freescale Semiconductor (type Symbol Min GV 1.7 DD 0.49 × ...

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... ILAC — 0.20 IHAC REF MV + 0.25 REF (typ)=1 Min Max Unit — 0 25° / OUT DD OUT = 25° / OUT DD OUT REF Max Unit μA — 1500 1250 Max Unit MV – 0.20 V REF MV – 0.25 V REF — V — V Freescale Semiconductor Notes Note 1 ...

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... Maximum DDR2 and DDR3 frequency is 667MHz. Figure 8 shows the DDR2 and DDR3 SDRAM interface input timing diagram. 3 MCK[n] MCK[n] MDQS[n] MDQ[x] MPC8535E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 3 Freescale Semiconductor of 1.5 V ± 5%. DDR3 data rate is between 606MHz and 667MHz. DD Symbol Min V — ...

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... DDKHCX 1.10 1.48 1.95 t DDKHMH –0.6 t DDKHDS, t DDKLDS 450 538 700 t DDKHDX, t DDKLDX 450 538 700 t DDKHMP Max Unit Notes — 7 — — — 7 — — — 7 — — — 7 — — 0 — 7 — — — 7 — — Freescale Semiconductor ...

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... Maximum DDR2 and DDR3 frequency is 667 MHz For the ADDR/CMD setup and hold specifications in Control register is set to adjust the memory clocks by 1/2 applied cycle. MPC8535E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 3 Freescale Semiconductor of 1.8 V ± 5% for DDR2 or 1.5 V ± 5% for DDR3 ...

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... Figure 10. DDR SDRAM Output Timing Diagram MPC8535E PowerQUICC III Integrated Processor Hardware Specifications, Rev MCK t DDKHMHmax DDKHMH(min) = –0.6 ns Figure 9. Timing Diagram for tDDKHMH t MCK t ,t DDKHAS DDKHCS t ,t DDKHAX DDKHCX NOOP t DDKHMP t DDKHMH t DDKHDS DDKHDX ). DDKHMH t DDKHME t DDKLDS t DDKLDX Freescale Semiconductor ...

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... AC timing specifications. Characteristic SPI_MOSI output—Master data hold time SPI_MOSI output—Master datadelay SPI_CS outputs—Master data hold time MPC8535E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 3 Freescale Semiconductor = 50 Ω Figure 11. DDR AC Test Load Table 20 ...

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... Note that although the specifications generally reference the rising edge of t NIIXKH t NIIVKH t NIKHOV t NIKHOV2 1 (continued) Min Max Unit Note — 6 — — ns for outputs. For example, memory clock reference (K) goes from SPI Ω NIKHOX t NIKHOX2 Freescale Semiconductor — — — ...

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... The middle of a start bit is detected as the 8 Subsequent bit values are sampled each 16 2.9 Ethernet: Enhanced Three-Speed Ethernet (eTSEC), MII Management This section provides the AC and DC electrical characteristics for enhanced three-speed and MII management. MPC8535E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 3 Freescale Semiconductor Symbol Min – ...

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... Section 2.9.3, “SGMII Interface Electrical Symbol Min Max LV 3.13 3. VOH 2.40 LV /TV DD VOL GND 0.50 V 1. –0.3 0. — –600 — IL and TV symbols referenced Characteristics.” The SGMII Unit Notes 0.3 V — — + 0.3 V — — μA 1, 2,3 3 μA Table 1 and Table 2. Freescale Semiconductor ...

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... A summary of the FIFO AC specifications appears in Table 26. FIFO Mode Transmit AC Timing Specification Parameter/Condition 2 TX_CLK, GTX_CLK clock period TX_CLK, GTX_CLK duty cycle TX_CLK, GTX_CLK peak-to-peak jitter MPC8535E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 3 Freescale Semiconductor Ethernet: Enhanced Three-Speed Ethernet (eTSEC), MII Management Symbol Min LV /TV 2.37 DD ...

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... Section 2.4.6, “Platform to FIFO Min Typ Max 6.0 8.0 100 — — 250 — — 0.75 — — 0.75 1.5 — — 0.5 — — Section 2.4.6, “Platform to FIFO t t FITF FITR Freescale Semiconductor Unit Unit ...

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... Data valid t to GTX_CLK Min Setup time is a function of clock period and max hold time. (Min Setup = Cycle time - GTKHDV Max Hold) MPC8535E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 3 Freescale Semiconductor Ethernet: Enhanced Three-Speed Ethernet (eTSEC), MII Management t FIR t FIRF ...

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... GMII (G) receive (RX) clock. For rise and fall times, the latter GRX = 50 Ω Figure 17. eTSEC AC Test Load t GTXR Min Typ Max — 8.0 — 35 — 65 2.0 — — 0 — — — — 1.0 — — 1.0 symbolizes GMII GRDVKH clock Ω L Freescale Semiconductor Unit ...

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... For example, the subscript of t convention is used with the appropriate letter: R (rise (fall). MPC8535E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 3 Freescale Semiconductor Ethernet: Enhanced Three-Speed Ethernet (eTSEC), MII Management t GRX ...

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... Note that, in general, the MRX = 50 Ω Figure 20. eTSEC AC Test Load t MTXR Min Typ Max — 400 — — 40 — 35 — 65 10.0 — — 10.0 — — 1.0 — 4.0 1.0 — 4.0 symbolizes MII receive MRDVKH clock reference (K) going MRX Ω Freescale Semiconductor Unit ...

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... F (fall). 2. Data valid t to GTX_CLK Min Setup time is a function of clock period and max hold time. (Min Setup = Cycle time - Max TTKHDV Hold) MPC8535E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 3 Freescale Semiconductor Ethernet: Enhanced Three-Speed Ethernet (eTSEC), MII Management t MRX t t ...

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... For example, t symbolizes TBI receive timing (TR) with TRDXKH clock reference (K) going to the high (H) TRX Freescale Semiconductor Unit TRDVKH ...

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... RX_CLK peak-to-peak jitter Rise time RX_CLK (20%–80%) Fall time RX_CLK (80%–20%) RCG[9:0] setup time to RX_CLK rising edge RCG[9:0] hold time to RX_CLK rising edge MPC8535E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 3 Freescale Semiconductor Ethernet: Enhanced Three-Speed Ethernet (eTSEC), MII Management t TRX t t ...

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... RGT t /t RGTH RGT RGTH RGT t RGTR t RGTF represents the TBI (T) receive (RX) clock. Note RGT t TRRR Min Typ Max –500 0 500 1.0 — 2.8 7.2 8.0 8.8 45 — — — 0.75 — — 0.75 of the lowest speed RGT Freescale Semiconductor Unit ...

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... Table 36. RMII Transmit AC Timing Specifications At recommended operating conditions with L/TV Parameter/Condition TSECn_TX_CLK clock period TSECn_TX_CLK duty cycle TSECn_TX_CLK peak-to-peak jitter MPC8535E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 3 Freescale Semiconductor Ethernet: Enhanced Three-Speed Ethernet (eTSEC), MII Management t RGTH t SKRGT_TX TXD[8:5] TXD[3:0] ...

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... For example RMTR 1 Symbol Min Typ Max t 15.0 20.0 25.0 RMR RMRH t — — 250 RMRJ t 1.0 — 2.0 RMRR Freescale Semiconductor Unit MTKHDX Unit ...

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... Recommendations,” as long as such termination does not violate the desired POR configuration requirement on these pins, if applicable. MPC8535E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 3 Freescale Semiconductor Ethernet: Enhanced Three-Speed Ethernet (eTSEC), MII Management of 3.3 V ± 5%. DD (first two letters of functional block)(signal)(state) (reference)(state) for outputs ...

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... In a frequency band from 150 kHz to 15 MHz, at BER of 10E-12. 3. Total peak-to-peak deterministic jitter “Dj” should be less than or equal to 50 ps. MPC8535E PowerQUICC III Integrated Processor Hardware Specifications, Rev Section 2.20, “High-Speed Min Typical Max Units Notes — 10 (8) — — — 100 ps — –50 — 2,3 Freescale Semiconductor ...

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... Typ column is based on the condition of X2V OD (VOS =550mV), SerDes2 transmitter is terminated with 100-Ω differential load between SD2_TX[n] and SD2_TX[n]. MPC8535E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 3 Freescale Semiconductor Ethernet: Enhanced Three-Speed Ethernet (eTSEC), MII Management Symbol Min X2V 0 ...

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... SD2_RXn C SD_TXm TX 50 Ω Ω SD2_RXn SD_TXm SD2_TXn 50 Ω 50 Ω 50 Ω 50 Ω SD2_TXn Symbol Min Typ X2V 0.95 1.0 DD — N/A V 100 — RX_DIFFp-p 175 — 50 Ω Receiver 50 Ω 50 Ω Transmitter 50 Ω Max Unit Notes 1.05 V — — 1 1200 Freescale Semiconductor ...

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... Total Jitter Unit Interval V fall time (80%-20 rise time (20%-80%) OD Notes: 1. Each UI is 800 ps ± 100 ppm. MPC8535E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 3 Freescale Semiconductor Ethernet: Enhanced Three-Speed Ethernet (eTSEC), MII Management Symbol Min Typ VLOS 30 — 65 — V — ...

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... DD Symbol Min JD 0.37 JDR 0.55 JSIN 0.1 JT 0.65 BER — UI 799. 0.275 0.4 Time (UI) Typ Max Unit — — UI p-p — — UI p-p — — UI p-p — — UI p-p -12 — 10 800 800. — 200 nF 0.6 0.725 Freescale Semiconductor Notes — ...

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... The output delay is count starting rising edge if t Figure 34 provides the data and command input timing diagram. TSEC_1588_CLK TSEC_1588_TRIG_IN Figure 34. eTSEC IEEE 1588 Input AC timing MPC8535E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 3 Freescale Semiconductor Ethernet: Enhanced Three-Speed Ethernet (eTSEC), MII Management t T1588CLKOUT t T1588CLKOUTH t T1588OV is non-inverting ...

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... TX_CLK Typ Max Unit Note T *7 — TX_CLK — — — 250 ps — — 2.0 ns — — 2.0 ns — — — ns — — 3.0 ns — — — which is the TX_CLK . is defined in terms of the T1588CLK will be T1588CLK Freescale Semiconductor ...

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... At recommended operating conditions with OVDD is 3.3 V ± 5%. Parameter/Condition EC_MDC frequency EC_MDC period EC_MDC clock pulse width high EC_MDC to EC_MDIO delay EC_MDIO to EC_MDC setup time MPC8535E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 3 Freescale Semiconductor Ethernet Management Interface Electrical Characteristics Table 44. Symbol Min OV 3.13 ...

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... For example, t CCB = 533/(2*4*8) = 533/64 = 8.3 MHz. MDC /448. See the MPC8536E reference manual’s . (Min Setup = Cycle MDKHDX t MDCR t MDDXKH Freescale Semiconductor Notes — — — MDKHDX ). The actual ...

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... This should not be a problem, because the PHY should not be functionally looking at these signals on that cycle as per ULPI specifications MPC8535E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 3 Freescale Semiconductor Table 46. USB DC Electrical Characteristics symbol referenced in IN Table 47 ...

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... Figure 37 provide the AC test load and signals for the USB, respectively. Output USB0_CLK/USB1_CLK/DR_CLK Input Signals Output Signals: MPC8535E PowerQUICC III Integrated Processor Hardware Specifications, Rev Ω Ω Figure 36. USB AC Test Load t USIVKH t t USKHOX USKHOV Figure 37. USB Signals USIXKH Freescale Semiconductor ...

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... High-level input voltage Low-level input voltage Input current 1 ( High-level output voltage (BV = min –1 mA Low-level output voltage (BV = min mA Note: 1. Note that the symbol BV IN MPC8535E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 3 Freescale Semiconductor Symbol symbol referenced in IN Symbol Min –0.3 ...

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... LBK LBKH/ LBK t 150 ps LBKSKEW t 1.8 — ns LBIVKH1 t 1.7 — ns LBIVKH2 t 1.0 — ns LBIXKH1 t 1.0 — ns LBIXKH2 t 1.5 — ns LBOTOT t — 2.3 ns LBKHOV1 t — 2.4 ns LBKHOV2 t — 2.3 ns LBKHOV3 t — 2.3 ns LBKHOV4 t 0.7 — ns LBKHOX1 Freescale Semiconductor μ Notes 2 — — ...

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... Local bus clock to address valid for LAD Local bus clock to LALE assertion Output hold from local bus clock (except LAD/LDP and LALE) MPC8535E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 3 Freescale Semiconductor (First two letters of functional block)(signal)(state) (reference)(state) for outputs. For example, t LBK ...

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... LBK LBKH/ LBK t 150 ps LBKSKEW t 2.4 — ns LBIVKH1 t 1.9 — ns LBIVKH2 t 1.1 — ns LBIXKH1 t 1.1 — ns LBIXKH2 t 1.2 — ns LBOTOT t — 3.2 ns LBKHOV1 t — 3.2 ns LBKHOV2 t — 3.2 ns LBKHOV3 t — 3.2 ns LBKHOV4 t 0.9 — ns LBKHOX1 Freescale Semiconductor Notes Notes — ...

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... BV /2. DD Figure 38 provides the AC test load for the local bus. Output MPC8535E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 3 Freescale Semiconductor Configuration Symbol — — — (First two letters of functional block)(signal)(state) (reference)(state) for outputs. For example, t ...

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... LCLK[n] and inputs signals are captured at the rising edge of LCLK[n] with the exception of LGTA/LUPWAIT (which is captured at the falling edge of the LCLK[n]). MPC8535E PowerQUICC III Integrated Processor Hardware Specifications, Rev LBIVKH1 t LBIVKH2 t LBKHOZ1 t t LBKHOV1 LBKHOX1 t LBKHOZ2 t t LBKHOV2 LBKHOX2 t LBKHOZ2 t t LBKHOV3 LBKHOX2 t LBOTOT t LBKHOV4 NOTE t LBIXKH1 t LBIXKH2 Freescale Semiconductor ...

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... Input hold from local bus clock (except LUPWAIT) LUPWAIT input hold from local bus clock LALE output transition to LAD/LDP output transition (LATCH hold time) Local bus clock to output valid (except LAD/LDP and LALE) MPC8535E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 3 Freescale Semiconductor t LBIVKL2 t LBKLOV1 t ...

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... LBKLOZ2 (First two letters of functional block)(signal)(state) (reference)(state) for outputs. For example, t symbolizes local bus LBIXKH1 clock reference (K) goes high (H), in this case for LBK clock reference ( high (H), with respect to the LBK LBOTOT Freescale Semiconductor Unit Notes 4,8 ...

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... LGTA UPM Mode Input Signal: LUPWAIT Input Signals: LAD[0:31]/LDP[0:3] UPM Mode Output Signals: LCS[0:7]/LBS[0:3]/LGPL[0:5] Figure 41. Local Bus Signals, GPCM/UPM Signals for LCRR[CLKDIV] = 4(PLL Enabled) MPC8535E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 3 Freescale Semiconductor t LBKHOZ1 t LBKHOV1 t LBIVKH2 t LBIVKH1 ...

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... MPC8535E PowerQUICC III Integrated Processor Hardware Specifications, Rev LBKHOZ1 t LBKHOV1 t LBIVKH2 t LBIVKH1 t LBKHOZ1 t LBKHOV1 Table 3) Condition — 0.625 * OVDD IH — — -100 uA @OVDDmin 0.75 * OVDD LBIXKH2 t LBIXKH1 Min Max Unit OVDD+0.3 V –0.3 0.25 * OVDD V – — V Freescale Semiconductor Notes — — — — ...

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... To satisfy hold timing, the delay difference between clock input and cmd/data input must not exceed 2ns. ≤10 pF, (1 card), and CARD L MPC8535E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 3 Freescale Semiconductor Enhanced Secure Digital Host Controller (eSDHC) Table 3) Condition I = 100uA @OVDDmin ...

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... Table 57. JTAG DC Electrical Characteristics Parameter High-level input voltage Low-level input voltage MPC8535E PowerQUICC III Integrated Processor Hardware Specifications, Rev SHSCK VM = Midpoint Voltage ( SHSIVKH t SHSKHOV VM = Midpoint Voltage (OV 1 Symbol Min -0 SHSCKL SHSCKH t t SHSCKF SHSCKR / SHSIXKH /2) DD Max Unit 0.8 V Freescale Semiconductor ...

Page 77

... TRST is an asynchronous level sensitive signal. The setup time is for test purposes only. 3.) The output timings are measured at the pins. All output timings assume a purely resistive 50-Ω load. Time-of-flight delays must be added for trace lengths, vias, and connectors in the system. MPC8535E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 3 Freescale Semiconductor 1 Symbol Min I — ...

Page 78

... MPC8535E PowerQUICC III Integrated Processor Hardware Specifications, Rev Ω JTKHKL t JTG VM = Midpoint Voltage ( TRST VM = Midpoint Voltage (OV DD /2) Figure 47. TRST Timing Diagram VM t JTDVKH t JTKLDV VM = Midpoint Voltage (OV DD /2) Figure 48. Boundary-Scan Timing Diagram Ω JTGR t JTGF JTDXKH Input Data Valid Output Data Valid Freescale Semiconductor ...

Page 79

... Only 100/125/150 MHz have been tested, other in between values will not work correctly with the rest of the system frequency band from 150 kHz to 15 MHz, at BER of 10E-12. 3. Total peak-to-peak deterministic jitter “Dj” should be less than or equal to 50 ps. Ref_CLK Figure 49. Reference Clock Timing Waveform MPC8535E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 3 Freescale Semiconductor Table 59. Symbol Min Typical ...

Page 80

... Max Units Notes — — Gbps — 670.2333 ps 335.1167 450 mV 3 — 600 mV 700 — 273 ps 136 20 ps — — ohm 115 — ohm — — — — — Freescale Semiconductor ...

Page 81

... Only applies when operating in 3.0Gb data rate mode. 2. The max value stated for 3.0 GHz - 5.0 GHz range only applies to Gen2i mode and not to Gen2m mode. 3. Only applies to Gen1i mode. MPC8535E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 3 Freescale Semiconductor Symbol Min Typical — ...

Page 82

... EARLY (TX+ is early) Min Typical Max 240 400 600 240 — 750 100 — 273 67 — 136 — — — — — — 115 40 — — 200 250 450 20% t SAT_TXSKEW Units Notes 1 mVp-p — ps — ps — ohm — ohm 5 mV Freescale Semiconductor ...

Page 83

... The max value stated for 3.0 GHz - 5.0 GHz range only applies to Gen2i mode and not to Gen2m mode. 4. The max value stated for 2.4 GHz - 3.0 GHz range only applies to Gen2i mode for Gen2m the value Only applies to Gen1i mode. MPC8535E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 3 Freescale Semiconductor Min Typical Max — ...

Page 84

... UI 480 — UI 160 — UI — 175 ns — 525 ns Min Max Unit 3. 0.3 × OV –0 0.2 × Freescale Semiconductor Notes — — — — — — — Notes — — — 1 ...

Page 85

... CBUS compatible masters Data output delay time Set-up time for STOP condition Rise time of both SDA and SCL signals Fall time of both SDA and SCL signals MPC8535E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 3 Freescale Semiconductor Electrical Characteristics (continued) of 3.3 V ± 5%. DD Symbol ...

Page 86

... OV — 0.2 × OV — symbolizes I I2DVKH clock reference (K) going to the I2C symbolizes I I2PVKH 2 C frequency calculation, refer to Determining ) of the SCL signal. I2CL Ω I2KHKL I2CF t I2CR t I2PVKH P Freescale Semiconductor Notes — — — timing 2 C clock I2C S ...

Page 87

... The minimum pulse width is a function of the MPX/Platform clock. The minimum pulse width must be greater than or equal to 4 times the MPX/Platform clock period. Figure 53 provides the AC test load for the GPIO. Output MPC8535E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 3 Freescale Semiconductor Symbol ...

Page 88

... OH V — OL symbol referenced in Table Symbol Min Max t — 6.0 PCKHOV t 2.0 — PCKHOX t — 14 PCKHOZ t 3.0 — PCIVKH t 0 — PCIXKH 10 × — PCRVRH SYS PCRHRX Max Unit + 0 0.8 V μA ±5 — V 0.4 V and Table 2. Unit Notes clocks Freescale Semiconductor ...

Page 89

... The reset assertion timing requirement for HRESET is 100 μs. Figure 54 provides the AC test load for PCI. Output Figure 55 shows the PCI input AC timing conditions. CLK Input Figure 55. PCI Input AC Timing Measurement Conditions MPC8535E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 3 Freescale Semiconductor 1 Symbol t PCRHFV t PCICLK t PCICLK for inputs and t (first two letters of functional block)(reference)(state)(signal)(state) , reference (K) going to the high (H) state or setup time ...

Page 90

... The V value can be either positive or negative. SDn_TX SDn_TX. OD (or Differential Input Swing defined as the difference of the two complimentary input The V value can be either positive or negative. SDn_RX SDn_RX. ID DIFFp = | Volts. DIFFp DIFFp-p = 2*V = DIFFp-p DIFFp Freescale Semiconductor ...

Page 91

... SerDes Reference Clock Receiver Reference Circuit Structure — The SDn_REF_CLK and SDn_REF_CLK are internally AC-coupled differential inputs as shown in Each differential clock input (SDn_REF_CLK or SDn_REF_CLK) has a 50-Ω termination to SGND (xcorevss) followed by on-chip AC-coupling. MPC8535E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 3 Freescale Semiconductor |. cm Differential Swing ...

Page 92

... DC exceeds the maximum input current limitations, then it must be AC-coupled off-chip. • The input amplitude requirement — This requirement is described in detail in the following sections. SDn_REF_CLK SDn_REF_CLK Figure 58. Receiver of SerDes Reference Clocks MPC8535E PowerQUICC III Integrated Processor Hardware Specifications, Rev Ω Input Amp 50 Ω Freescale Semiconductor ...

Page 93

... Input Amplitude or Differential Peak < 800 _REF_CLK SD n _REF_CLK Figure 59. Differential Reference Clock Input DC Requirements (External DC-Coupled) MPC8535E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 3 Freescale Semiconductor High-Speed Serial Interfaces Figure 60 shows the SerDes reference clock input requirement for Figure 61 100 mV < ...

Page 94

... MPC8535E SerDes reference clock receiver requirement provided in this document. MPC8535E PowerQUICC III Integrated Processor Hardware Specifications, Rev NOTE below are for conceptual reference only. Due to the fact that clock Vmax < Vcm + 400 mV Vcm Vmin > Vcm – 400 mV 0V Freescale Semiconductor ...

Page 95

... Clock Driver Clock Driver CLK_Out 10 nF Figure 63. AC-Coupled Differential Connection with LVDS Clock Driver (Reference Only) MPC8535E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 3 Freescale Semiconductor SD n _REF_CLK 100 Ω differential PWB trace SD n _REF_CLK Clock driver vendor dependent source termination resistor SD n _REF_CLK 100 Ω ...

Page 96

... SDn_REF_CLK 10nF R2 100 Ω differential PWB trace SDn_REF_CLK Ω. Assume clock driver’s Total 50 output impedance is about 16 Ω. SDn_REF_CLK 100 Ω differential PWB trace SDn_REF_CLK 50 Ω MPC8535E 50 Ω SerDes Refer. CLK Receiver 50 Ω 50 Ω SerDes Refer. CLK Receiver 50 Ω Freescale Semiconductor ...

Page 97

... Rise Edge Rate V = +200 –200 mV IL – _REF_CLK SD n _REF_CLK Figure 66. Differential Measurement Points for Rise and Fall Time MPC8535E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 3 Freescale Semiconductor 1.0V ± 5%. DD_SRDS1 DD_SRDS2 Symbol Rise Edge Rate Fall Edge Rate Rise-Fall ...

Page 98

... Please note that external AC Coupling capacitor is required for the above three serial transmission protocols with the capacitor value defined in specification of each protocol section. MPC8535E PowerQUICC III Integrated Processor Hardware Specifications, Rev Clocks” SD1_RXn or SD1_TXn or SD2_RXn SD2_TXn 50 Ω 50 Ω SD1_TXn or SD1_RXn or SD2_TXn SD2_RXn SD2_REF_CLK” 50 Ω Receiver 50 Ω Freescale Semiconductor ...

Page 99

... Symbol Parameter UI Unit Interval V Differential TX-DIFFp-p Peak-to-Peak Output Voltage MPC8535E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 3 Freescale Semiconductor Min Nom Max Units 399.88 400 400.12 ps Each UI is 400 ps ± 300 ppm. UI does not account for Spread Spectrum Clock dictated variations. See Note 1 ...

Page 100

... TX-DIFFp-p of the TX-DIFFp – 0.3 UI. TX-EYE = relation to a TX-DIFFp-p = RMS(|V +V |/2 – V TXD+ TXD- TX-CM- |/2 (avg) TX-D+ TX-D- – V TX-CM-Idle-DC (During Electrical = |/2 [L0] (avg) TX-D+ TX- |/2 (avg) TX-D+ TX-D- – < TX-CM-DC- (avg) TX- (avg) TX- < TX-IDLE-D+ TX-IDLE-D- Freescale Semiconductor ) ...

Page 101

Table 71. Differential Transmitter (TX) Output Specifications (continued) Symbol Parameter T Maximum time to TX-IDLE-SET-TO-IDLE transition to a valid electrical idle after sending an electrical Idle ordered set T Maximum time to TX-IDLE-TO-DIFF-DATA transition to valid TX specifications after leaving ...

Page 102

... NOTE Min Nom Max Units 399.8 400 400. 0.175 — 1.200 V Figure 71) in place of Comments Each UI is 400 ps ± 300 ppm. UI does not account for Spread Spectrum Clock dictated variations. See Note 2*|V – RX-DIFFp-p RX-D+ RX-D- See Note 2. Freescale Semiconductor ...

Page 103

Table 72. Differential Receiver (RX) Input Specifications (continued) Symbol Parameter T Minimum RX-EYE Receiver Eye Width T Maximum time RX-EYE-MEDIAN-to-MAX between the jitter -JITTER median and maximum deviation from the median Peak RX-CM-ACp Common Mode Input Voltage RL ...

Page 104

... SKP ordered set (for example, COM and one to five Symbols) at the RX as well as any delay differences arising from the interconnect itself. Figure 71 should be used Figure 70). If the specification ensures a jitter distribution in Figure 71) in place of Figure 71) will Freescale Semiconductor ...

Page 105

... Figure 71. Compliance Test/Measurement Load 2.23 Clocking This section describes the PLL configuration of the MPC8535E. Note that the platform clock is identical to the core complex bus (CCB) clock. MPC8535E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 3 Freescale Semiconductor NOTE Figure 71. NOTE Pin Pin ...

Page 106

... MHz 1250 MHz Unit Min Max Min Max 600 1000 600 1250 MHz 333 400 333 500 400 400 400 500 Ratio,“and Section 2.23.4, Unit Notes MHz Ratio,” and Section 2.23.4, “DDR/DDRCLK PLL Freescale Semiconductor Notes 1, 2 ...

Page 107

... In asynchronous mode, the DDR PLL rate to DDRCLK ratios listed in since the DDR PLL rate in asynchronous mode means the DDR data rate resulting from DDR PLL output. MPC8535E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 3 Freescale Semiconductor Table 75: Table 75. CCB Clock Ratio ...

Page 108

... PCI1_CLK is required as a separate PCI clock source, asynchronous with respect to SYSCLK. MPC8535E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 3 108 Table 77. DDR Clock Ratio Reset Configuration Value (Binary) Name 000 001 010 011 cfg_ddr_pll[0:2] 100 101 110 111 DDR:DDRCLK Ratio 3:1 4:1 6:1 8:1 10:1 12:1 Reserved Synchronous mode Freescale Semiconductor ...

Page 109

... Thermal Characteristics Table 79 provides the package thermal characteristics. Characteristic Junction-to-ambient Natural Convection Junction-to-ambient Natural Convection Junction-to-ambient (@200 ft/min) MPC8535E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 3 Freescale Semiconductor SYSCLK (MHz) 41.66 66.66 83 Platform /CCB Frequency (MHz) 333 333 415 400 ...

Page 110

... Temperature dependent 7.5 Substrate (29 × 29 × 1.2 mm) 19.8 19.8 1.13 Solder and Air (29 × 29 × 0.5 mm) 0.034 0.034 12.1 Symbol Value Unit Notes °C θJA °C θJB °C/W R < 0.1 4 θJC C/W Units — W/m•K W/m•K W/m•K Freescale Semiconductor ...

Page 111

... This section provides thermal management information for the flip chip plastic ball grid array (FC-PBGA) package for air-cooled applications. Proper thermal control design is primarily dependent on the system-level design—the heat sink, airflow, and thermal interface material. MPC8535E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 3 Freescale Semiconductor Thermal 111 ...

Page 112

... Figure FC-PBGA Package Heat Sink Heat Sink Clip Die Table 70, the intrinsic internal conduction thermal resistance paths are as follows: Radiation Convection Heat Sink Radiation Convection 73. The heat sink should be attached to the Thermal Interface Material Die/Package Die Junction Package/Solder Spheres Freescale Semiconductor ...

Page 113

... Each circuit should be placed as close as possible to the specific AV nearby circuits. It should be possible to route directly from the capacitors to the AV FC-PBGA the footprint, without the inductance of vias. MPC8535E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 3 Freescale Semiconductor _SRDS respectively). The AV level should always be equivalent through a low frequency filter scheme such as the following ...

Page 114

... DD _SRDSn balls. The 0.003-µF capacitor is closest to the balls, DD 1.0 Ω 2.2 µF 2.2 µF GND . DD power plane. DD Table 1. See the MPC8536E PowerQUICC III Integrated Processor Reference Manual AV DD Figure 76. For maximum AV SRDS DD - 0.003 µ DD Freescale Semiconductor , ...

Page 115

... Output Buffer DC Impedance The MPC8535E drivers are characterized over process, voltage, and temperature. For all buses, the driver is a push-pull single-ended driver type (open drain for I MPC8535E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 3 Freescale Semiconductor SerDes Block Power Supply Decoupling Recommendations , ...

Page 116

... Target (cfg_pci_impd= GND. Then, the DD 77). The output impedance is the average of two DD SW2 SW1 , nominal OV DD DDR DRAM Symbol Unit 18 Target (full strength mode) 36 Target (full strength mode) 18 Target (full strength mode) 36 Target (full strength mode) Freescale Semiconductor and Ω Ω ...

Page 117

... No pull-up/pull-down is required for TDI, TMS, or TDO. MPC8535E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 3 Freescale Semiconductor allows the COP port to independently assert HRESET or TRST, while ensuring that the Figure 79, for connection to the target system, and is based on the 0.025" ...

Page 118

... COP_TRST 10 Ω 2 COP_VDD_SENSE NC COP_CHKSTP_OUT 10 kΩ COP_CHKSTP_IN COP_TMS COP_TDO COP_TDI COP_TCK Figure 78. JTAG Interface Connection kΩ 6 SRESET 1 10 kΩ HRESET 10 kΩ 10 kΩ 10 kΩ 10 kΩ 1 TRST CKSTP_OUT 10 kΩ CKSTP_IN TMS TDO TDI TCK 10 kΩ Freescale Semiconductor ...

Page 119

... If only part of the high speed SerDes interface pins are used, the remaining high-speed serial I/O pins should be terminated as described in this section. The following pins must be left unconnected (float) if not used: • SD1_TX[7:4] • SD1_TX[7:4] • Reserved pins: T22, T23 MPC8535E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 3 Freescale Semiconductor Guidelines for High-Speed Interface Termination 2 COP_TDO COP_TDI 3 4 ...

Page 120

... SerDes 2 block for power saving. Note that both S2VDD and X2VDD must remain powered. 4 Ordering Information Ordering information for the parts fully covered by this specification document is provided in Addressed by This Document.” MPC8535E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 3 120 Section 4.1, “Part Numbers Fully Freescale Semiconductor ...

Page 121

... Additionally, parts addressed by part number specifications may support other maximum core frequencies. 3. See Table 84 for the corresponding maximum platform frequency. MPC8535E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 3 Freescale Semiconductor Part Numbers Fully Addressed by This Document Table 82. Device Nomenclature ...

Page 122

... ATWLYYWW MMMMM CCCCC YWWLAZ FC-PBGA Standard Temp Without Security MPC8535AVTAKG(A) MPC8535EAVTAKG(A) MPC8535AVTANG(A) MPC8535EAVTANG(A) MPC8535AVTAQG(A) MPC8535EAVTAQG(A) MPC8535AVTATH(A) MPC8535EAVTATH(A) Standard Temp Extended Temp With Security Without Security Standard Temp Notes With Security — — — — Extended Temp With Security Freescale Semiconductor Notes 1 ...

Page 123

... Package outline Interconnects Pitch Minimum module height Maximum module height Solder Balls Ball diameter (typical) MPC8535E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 3 Freescale Semiconductor Package Parameters for the MPC8535E FC-PBGA FC-PBGA MPC8535E 29 mm × 783 1 mm 2. ...

Page 124

... The mechanical dimensions and bottom surface nomenclature of the MPC8535E, 783 FC-PBGA package are shown in Figure 81. Figure 81. Mechanical Dimensions and Bottom Surface Nomenclature of the MPC8535E FC-PBGA 1. All dimensions are in millimeters. 2. Dimensions and tolerances per ASME Y14.5M-1994. MPC8535E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 3 124 FC-PBGA MPC8535E NOTES for Figure 81 Freescale Semiconductor ...

Page 125

... Table 5, ”MPC8535E Power Dissipation 5,” changed an “—”’ to “0.” 0 08/2009 • Initial public release. MPC8535E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 3 Freescale Semiconductor Mechanical Dimensions of the MPC8535E FC-PBGA Table 85. Document Revision History Substantive Change(s) Table 21 Figure 25, “RGMII and RTBI AC Timing and Multiplexing Diagrams.” ...

Page 126

... Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer ...