MPC8536-RDK Freescale Semiconductor, MPC8536-RDK Datasheet

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... Two IEEE Std 802.3®, IEEE 802.3u, IEEE 802.3x, IEEE 802.3z, IEEE 802.3ac, IEEE 802.3ab, and IEEE Std 1588™-compatible controllers © 2010 Freescale Semiconductor, Inc. All rights reserved. Document Number: MPC8536EEC MAPBGA–783 – Support for various Ethernet physical interfaces: GMII, TBI, RTBI, RGMII, MII, RGMII, RMII, and SGMII – ...

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... JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77 2.16 Serial ATA (SATA . .85 2.18 GPIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88 2.19 PCI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89 2.20 High-Speed Serial Interfaces . . . . . . . . . . . . . . . . . . . .91 MPC8536E PowerQUICC III Integrated Processor Hardware Specifications, Rev Table of Contents 2.21 PCI Express 100 2.23 Clocking 106 2.24 Thermal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 3 Hardware Design Considerations . . . . . . . . . . . . . . . . . . . . 114 3.1 System Clocking ...

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... The naming convention of TSEC1 and TSEC3 is used to allow the splitting voltage rails for the eTSEC blocks and to ease the port of existing PowerQUICC III software The UART_SOUT[0:1] and TEST_SEL pins must be set to a proper state during POR configuration. Please refer to MPC8536E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 3 Freescale Semiconductor e500 Core 512-Kbyte ...

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... Pin Map 1.1 Pin Map Figure 2 provides a bottom view of the pin map of the MPC8536E MDQ MDQ MDQ MDQ MDQS GND [5] [32] [46] [47] [34] MDQ MDQ MDM MDQS MDQ MDQ MDQ [44] [40] [5] [5] [42] [43] [35] MDQ MDQ MCS MDQ MDQ GND GND [45] [41] [0] [33] ...

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... MA MA MECC 12 GND [11] [9] [7] MBA MECC MDQS MAPAR_ 13 [2] [6] [8] ERR MDQ MECC GND [27] [1] MPC8536E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 3 Freescale Semiconductor MDQ MDQ MDQ MDQ GND [46] [47] [34] [56] MDQ MDQ MDQ MDQ GV DD [42] [43] [35] [60] MDQ MDQ ...

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... TSEC3_ TSEC3_ MSRCID X2GND TXD RXD [2] [7] [7] TSEC3_ VDD_ GND MDVAL RXD CORE [6] VDD_ VDD_ GND GND CORE CORE MPC8536E PowerQUICC III Integrated Processor Hardware Specifications, Rev TSEC1_ TSEC1_ TSEC1_ USB1_D USB1_D RXD TX_EN RX_DV [0] [2] [1] TSEC1_ TSEC1_ TSEC1_ USB1_D USB1_D ...

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... GND [0] [1] [25] LDP LSYNC_ 27 GND GND [2] IN AVDD_ LSYNC_ 28 MVREF GND LBIU OUT MPC8536E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 3 Freescale Semiconductor DETAIL C MDIC GV DD GND GND GND [0] LCS5/ LCS6/ MDQ LCS DMA_ DMA_ GND [18] [4] DREQ2 DACK2 MDQS MDQ ...

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... TPA SD1_ AGND_ SD1_RX SV DD REF_ SRDS [2] CLK SD1_ SD1_ SD1_RX SGND REF_ PLL_ [2] CLK TPD MPC8536E PowerQUICC III Integrated Processor Hardware Specifications, Rev DETAIL D PCI1_ PCI1_ PCI1_REQ PCI1_GNT CLK_ AD AD [3]/GPIO [3]/GPIO OUT [31] [28] [0] [2] PCI1_ PCI1_ PCI1_ PCI1_ OV DD ...

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... Table 1 provides the pin-out listing for the MPC8536E 783 FC-PBGA package. Signal PCI1_AD[31:0] Muxed Address / data PCI1_C_BE[3:0] Command/Byte Enable PCI1_PAR Parity PCI1_FRAME Frame PCI1_TRDY Target Ready PCI1_IRDY Initiator Ready PCI1_STOP Stop PCI1_DEVSEL Device Select PCI1_IDSEL Init Device Select PCI1_PERR Parity Error ...

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... Clock Enable MCK[0:5] Differential Clock 3 Pairs / DIMM MCK[0:5] Differential Clock 3 Pairs / DIMM MODT[0:3] On Die Termination MDIC[0:1] Calibration MPC8536E PowerQUICC III Integrated Processor Hardware Specifications, Rev Signal Name Package Pin Number DDR SDRAM Memory Interface A26,B26,C22,D21,D25, B25,D22,E21,A24,A23, B20,A20,A25,B24,B21, A21,E19,D19,E16,C16, F19,F18,F17,D16,B18, A18,A15,B14,B19,A19, A16,B15,D1,F3,G1,H2, ...

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... UPM general purpose line 5 / Amux LCLK[0:2] Local bus clock LSYNC_IN Synchronization LSYNC_OUT Local bus DLL DMA_DACK[0:1] DMA Acknowledge /GPIO[10:11] MPC8536E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 3 Freescale Semiconductor Signal Name Package Pin Number K22,L21,L22,K23,K24, L24,L25,K25,L28,L27, K28,K27,J28,H28,H27, G27,G26,F28,F26,F25, E28,E27,E26,F24,E24, C26,G24,E23,G23,F22, G22,G21 ...

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... USB2_PCTL0/GPIO[8] USB2 Port control 0 USB2_PCTL1/GPIO[9] USB2 Port control 1 USB2_CLK USB2 bus clock USB3_D[7:0] USB3 Data bits USB3_NXT USB3 Next data MPC8536E PowerQUICC III Integrated Processor Hardware Specifications, Rev Signal Name Package Pin Number AB10,AD11 AA11,AB11 J16 L18 AE13 AD13 USB Port 1 ...

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... TSEC1_RXD[7:0] Receive data TSEC1_RX_DV Receive data valid TSEC1_RX_ER Receive data error TSEC1_RX_CLK Receive clock Three-Speed Ethernet Controller (Gigabit Ethernet 3) MPC8536E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 3 Freescale Semiconductor Signal Name Package Pin Number AG8 AH8 AH9 AH5 Programmable Interrupt Controller ...

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... SDHC_WP/GPIO[5] Card write protection SPI_MOSI Master Out Slave In SPI_MISO Master In Slave Out SPI_CLK eSPI clock SPI_CS[0:3] / eSPI chip select / SDHC 8-bit SDHC_DAT[4:7] MMC data MPC8536E PowerQUICC III Integrated Processor Hardware Specifications, Rev Signal Name Package Pin Number T12,V8,U8,V9,T8,T7, T5, U10 U5 T10 T9 U12,U13,U6,V6,V1,U3, ...

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... Receive data(+) SD2_RX[1:0] Receive data(-) SD2_PLL_TPD PLL test point Digital SD2_REF_CLK PLL Reference clock SD2_REF_CLK PLL Reference clock complement Reserved MPC8536E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 3 Freescale Semiconductor Signal Name Package Pin Number DUART AE11,Y12 AB12,AD12 AC12,AF12 AF10,AA12 interface ...

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... Memory debug source port ID V12, W14,W11 MDVAL Memory debug data valid CLK_OUT Clock Out RTC Real time clock SYSCLK System clock / PCI clock DDRCLK DDR clock MPC8536E PowerQUICC III Integrated Processor Hardware Specifications, Rev Signal Name Package Pin Number — L9 General-Purpose Input/Output Y15,AE15 AA15,AC14 AH11 AC3 ...

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... General I/O supply PVDD LVDD GMAC 1 I/O supply TVDD GMAC 3 I/O supply GVDD SSTL2 DDR supply BVDD Local bus I/O supply MPC8536E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 3 Freescale Semiconductor Signal Name Package Pin Number JTAG AG28 AH28 AF28 AH27 AH21 ...

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... Local Bus PLL supply AVDD_PCI1 PCI PLL supply AVDD_SRDS SerDes 1 PLL supply AVDD_SRDS2 SerDes 2 PLL supply SENSEVDD_CORE SENSEVDD_PLAT GND Ground MPC8536E PowerQUICC III Integrated Processor Hardware Specifications, Rev Signal Name Package Pin Number M27,N25,P28,R24, R26,T24,T27,U25, W24,W26,Y24,Y27, AA25,AB28,AD27 M21,N23,P20,R22,T20, U23,V21,W22,Y20, AA23 R6,N7,M9 ...

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... SD1_PLL_TPA PLL test point analog SD2_IMP_CAL_RX Rx impedance calibration SD2_IMP_CAL_TX Tx impedance calibration SD2_PLL_TPA PLL test point analog Reserved Reserved NC MPC8536E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 3 Freescale Semiconductor Signal Name Package Pin Number M20,M24,N22,P21, R23,T21,U22,V20, W23, Y21 M28,N26,P24,P27, R25,T28,U24,U26,V24, W25,Y28,AA24,AA26, AB24,AB27,AD28 ...

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... TSEC1_TXD[3], TSEC3_TXD[7], HRESET_REQ, TRIG_OUT/READY/QUIESCE, MSRCID[2:4], ASLEEP. 23. This pin requires an external 4.7-kΩ pull-down resistor to prevent PHY from seeing a valid Transmit Enable before it is actively driven. 24. General-Purpose POR configuration of user system. MPC8536E PowerQUICC III Integrated Processor Hardware Specifications, Rev Signal Name Package Pin Number Ratio.” ...

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... POR setting cfg_ddr_pll[0:2]=111, the DDRCLK input is not required recommended to tie it off to GND when DDR controller is running in synchronous mode. See the MPC8536E PowerQUICC III Integrated Host Processor Family Reference Manual , Rev.0, Table 4-3 in section 4.2.2 “Clock Signals”, section 4.4.3.2 “ ...

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... Proper device operation outside these conditions is not guaranteed. Table 3. Recommended Operating Conditions Characteristic Core supply voltage Platform supply voltage PLL core supply voltage PLL other supply voltage MPC8536E PowerQUICC III Integrated Processor Hardware Specifications, Rev (continued) Symbol XV X2V ...

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... Caution: OVIN must not exceed OVDD by more than 0.3 V. This limit may be exceeded for a maximum during power-on reset and power-down sequences. 5. Caution: L/TV must not exceed L/TV IN power-on reset and power-down sequences. 6. Minimum temperature is specified with T MPC8536E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 3 Freescale Semiconductor Symbol (eTSEC1) (eTSEC3 USB, eSDHC, ...

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... Overall DC Electrical Characteristics Figure 2 shows the undershoot and overshoot voltages at the interfaces of the MPC8536E. B/G/L/OV DD B/G/L/OV B/G/L/ GND – 0 GND – 0.7 V Note refers to the clock period associated with the respective interface: CLOCK 2 For I C and JTAG, t For DDR, t For eTSEC, t ...

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... The drive strength of the PCI interface is determined by the setting of the PCI1_GNT1 signal at reset. 3. The drive strength of the DDR2 or DDR3 interface in half-strength mode 2.2 Power Sequencing The MPC8536E requires its power rails to be applied in a specific sequence in order to ensure proper device operation. These requirements are as follows for power up ...

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... Maximum (A) Thermal (W) Typical (W) Doze (W) 800 400 Nap (W) Sleep (W) Deep Sleep (W) Maximum (A) Thermal (W) Typical (W) Doze (W) 1000 400 Nap (W) Sleep (W) Deep Sleep (W) MPC8536E PowerQUICC III Integrated Processor Hardware Specifications, Rev Table 5. MPC8536E Power Dissipation V Junction Platfor Tempera 5 Core cy m ture (V) (V) (°C) 105 /90 400 1 ...

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... Maximum (A) 1250 500 Thermal (W) Typical (W) Doze (W) Nap (W) Sleep (W) Deep Sleep (W) Maximum (A) 1333 533 Thermal (W) Typical (W) Doze (W) Nap (W) Sleep (W) Deep Sleep (W) MPC8536E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 3 Freescale Semiconductor V Junction Platfor Tempera 5 Core cy m ture (V) (V) (°C) 105 500 1.0 1 ...

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... Table 3) while running a smoke test which includes an entirely Table 3) while running the Dhrystone benchmark. Table 3) for Commercial Tier pins. DD_PLAT Options,” for the full range of CCB frequencies that MPC8536E 5 Core Power Platform Power 7 7 mean Max mean Max — ...

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... Input Clocks 2.4.1 System Clock Timing Table 6 provides the system clock (SYSCLK) AC timing specifications for the MPC8536E. At recommended operating conditions (see Parameter/Condition SYSCLK frequency SYSCLK cycle time SYSCLK rise and fall time SYSCLK duty cycle SYSCLK jitter Notes: 1. Caution: The CCB clock to SYSCLK ratio and e500 core to CCB clock ratio settings must be chosen such that the resulting SYSCLK frequency, e500 (core) frequency, and CCB clock frequency do not exceed their respective maximum or minimum operating frequencies ...

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... Input Clocks 2.4.4 eTSEC Gigabit Reference Clock Timing Table 8 provides the eTSEC gigabit reference clocks (EC_GTX_CLK125) AC timing specifications for the MPC8536E. Table 8. EC_GTX_CLK125 AC Timing Specifications Parameter/Condition EC_GTX_CLK125 frequency EC_GTX_CLK125 cycle time EC_GTX_CLK rise and fall time LV TV 2.5V DD 3.3V DD EC_GTX_CLK125 duty cycle ...

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... For information on the input clocks of other functional blocks of the platform such as SerDes, and eTSEC, see the specific section of this document. 2.5 RESET Initialization This section describes the AC electrical specifications for the RESET initialization timing requirements of the MPC8536E. Table 10 provides the RESET initialization AC timing specifications for the DDR SDRAM component(s). Table 10. RESET Initialization Timing Specifications ...

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... DDR2 and DDR3 SDRAM 2.6 DDR2 and DDR3 SDRAM This section describes the DC and AC electrical specifications for the DDR SDRAM interface of the MPC8536E. Note that DDR2 SDRAM is GV (type) = 1.8 V and DDR3 SDRAM 2.6.1 DDR2 and DDR3 SDRAM DC Electrical Characteristics Table 12 provides the recommended operating conditions for the DDR SDRAM component(s) of the MPC8536E when interfacing to DDR2 SDRAM ...

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... AC timing specifications described in this section for DDR3 is applicable for data rate between 606 MHz and 667 MHz, as long as the DC and AC specifications of the DDR3 memory to be used are compliant to both JEDEC specifications as well as the specifications and requirements described in this MPC8536E hardware specifications document. 2.6.2.1 ...

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... Maximum DDR2 and DDR3 frequency is 667MHz. Figure 8 shows the DDR2 and DDR3 SDRAM interface input timing diagram. 3 MCK[n] MCK[n] MDQS[n] MDQ[x] MPC8536E PowerQUICC III Integrated Processor Hardware Specifications, Rev 1.5 V ± 5%. DDR3 data rate is between 606MHz and 667MHz. DD Symbol Min V — ...

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... MHz 533 MHz 400 MHz MDQ/MECC/MDM output hold with respect to MDQS 667 MHz 533 MHz 400 MHz MDQS preamble start MPC8536E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 3 Freescale Semiconductor of 1.8 V ± 5% for DDR2 or 1.5 V ± 5% for DDR3 Symbol Min t 3.0 ...

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... DQSS override bits in the TIMING_CFG_2 register. This will typically be set to the same delay as the clock adjust in the CLK_CNTL register. The timing parameters listed in the table assume that these 2 parameters have been set to the same adjustment value. See the MPC8536E PowerQUICC III Integrated Processor Reference Manual for a description and understanding of the timing modifications enabled by use of these bits. ...

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... MDQS Figure 10 shows the DDR SDRAM output timing diagram. MCK[n] MCK[n] ADDR/CMD Write A0 MDQS[n] MDQ[x] Figure 10. DDR SDRAM Output Timing Diagram MPC8536E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 3 Freescale Semiconductor t MCK t DDKHMHmax DDKHMH(min) = –0.6 ns Figure 9. Timing Diagram for tDDKHMH t MCK ...

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... Figure 11 provides the AC test load for the DDR bus. Output 2.7 eSPI This section describes the DC and AC electrical specifications for the eSPI of the MPC8536E. 2.7.1 eSPI DC Electrical Characteristics Table 20 provides the DC electrical characteristics for the device eSPI. Characteristic Output high voltage ...

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... SPIMISO (See Note) Output Signals: SPIMOSI (See Note) Output Signals: SPI_CS[0:3] (See Note) Note: The clock edge is selectable on SPI. Figure 13. SPI AC Timing in Master mode (Internal Clock) Diagram MPC8536E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 3 Freescale Semiconductor 2 Symbol t NIKHOV2 t NIIVKH t NIIXKH ...

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... DUART 2.8 DUART This section describes the DC and AC electrical specifications for the DUART interface of the MPC8536E. 2.8.1 DUART DC Electrical Characteristics Table 22 provides the DC electrical characteristics for the DUART interface. Table 22. DUART DC Electrical Characteristics Parameter High-level input voltage Low-level input voltage Input current ...

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... TV supports eTSECs The symbol this case, represents the LV IN MPC8536E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 3 Freescale Semiconductor Ethernet: Enhanced Three-Speed Ethernet (eTSEC), MII Management Section 2.10, “Ethernet Management Interface Electrical Section 2.9.3, “SGMII Interface Electrical Symbol Min Max LV 3 ...

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... For more information see A summary of the FIFO AC specifications appears in Table 26. FIFO Mode Transmit AC Timing Specification Parameter/Condition 2 TX_CLK, GTX_CLK clock period TX_CLK, GTX_CLK duty cycle TX_CLK, GTX_CLK peak-to-peak jitter MPC8536E PowerQUICC III Integrated Processor Hardware Specifications, Rev Symbol Min LV /TV 2.37 DD ...

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... Restrictions,” for more detailed description. Timing diagrams for FIFO appear in GTX_CLK t FITH TXD[7:0] TX_EN TX_ER Figure 14. FIFO Transmit AC Timing Diagram MPC8536E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 3 Freescale Semiconductor Ethernet: Enhanced Three-Speed Ethernet (eTSEC), MII Management Symbol t FITR t FITF 1 t ...

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... R (rise (fall). 2. Data valid t to GTX_CLK Min Setup time is a function of clock period and max hold time. (Min Setup = Cycle time - GTKHDV Max Hold) MPC8536E PowerQUICC III Integrated Processor Hardware Specifications, Rev FIR t ...

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... For example, the subscript of t convention is used with the appropriate letter: R (rise (fall). Figure 17 provides the AC test load for eTSEC. Output MPC8536E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 3 Freescale Semiconductor Ethernet: Enhanced Three-Speed Ethernet (eTSEC), MII Management t GTX t ...

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... MTX general, the clock reference symbol representation is based on two to three letters representing the clock of a particular functional. For example, the subscript of t convention is used with the appropriate letter: R (rise (fall). MPC8536E PowerQUICC III Integrated Processor Hardware Specifications, Rev GRX t ...

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... MII (M) receive (RX) clock. For rise and fall times, the latter convention is used with the MRX appropriate letter: R (rise (fall). Figure 20 provides the AC test load for eTSEC. Output MPC8536E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 3 Freescale Semiconductor Ethernet: Enhanced Three-Speed Ethernet (eTSEC), MII Management t MTX t ...

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... TBI (T) transmit (TX) clock. For rise and fall times, the latter convention is used with the appropriate letter: R (rise (fall). 2. Data valid t to GTX_CLK Min Setup time is a function of clock period and max hold time. (Min Setup = Cycle time - Max TTKHDV Hold) MPC8536E PowerQUICC III Integrated Processor Hardware Specifications, Rev MRX t t ...

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... The signals “TBI Receive Clock 0” and “TBI Receive Clock 1” refer to TSECn_RX_CLK and TSECn_TX_CLK pins respectively. These two clock signals are also referred as PMA_RX_CLK[0:1]. MPC8536E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 3 Freescale Semiconductor Ethernet: Enhanced Three-Speed Ethernet (eTSEC), MII Management ...

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... RX_CLK clock period RX_CLK duty cycle RX_CLK peak-to-peak jitter Rise time RX_CLK (20%–80%) Fall time RX_CLK (80%–20%) RCG[9:0] setup time to RX_CLK rising edge RCG[9:0] hold time to RX_CLK rising edge MPC8536E PowerQUICC III Integrated Processor Hardware Specifications, Rev TRX t t TRXH TRXF ...

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... Duty cycle may be stretched/shrunk during speed changes or while transition to a received packet's clock domains as long as the minimum duty cycle is not violated and stretching occurs for no more than three t transitioned between. MPC8536E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 3 Freescale Semiconductor Ethernet: Enhanced Three-Speed Ethernet (eTSEC), MII Management Figure 24 ...

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... RMII Transmit AC Timing Specifications The RMII transmit AC timing specifications are in Table 36. RMII Transmit AC Timing Specifications At recommended operating conditions with L/TV Parameter/Condition TSECn_TX_CLK clock period TSECn_TX_CLK duty cycle TSECn_TX_CLK peak-to-peak jitter MPC8536E PowerQUICC III Integrated Processor Hardware Specifications, Rev RGTH t SKRGT_TX TXD[8:5] TXD[3:0] ...

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... Table 37. RMII Receive AC Timing Specifications At recommended operating conditions with L/TV Parameter/Condition TSECn_RX_CLK clock period TSECn_RX_CLK duty cycle TSECn_RX_CLK peak-to-peak jitter Rise time TSECn_RX_CLK (20%–80%) MPC8536E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 3 Freescale Semiconductor Ethernet: Enhanced Three-Speed Ethernet (eTSEC), MII Management of 3.3 V ± 5 Symbol ...

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... RXD[1:0] CRS_DV RX_ER 2.9.3 SGMII Interface Electrical Characteristics Each SGMII port features a 4-wire AC-Coupled serial link from the dedicated SerDes 2 interface of MPC8536E as shown in Figure 29, where C is the external (on board) AC-Coupled capacitor. Each output pin of the SerDes transmitter differential TX pair features 50-Ω output impedance. Each input of the SerDes receiver differential pair features 50-Ω on-die termination to S2GND (xcorevss). The reference circuit of the SerDes transmitter and receiver is shown in When an eTSEC port is configured to operate in SGMII mode, the parallel interface’ ...

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... MHz SerDes2 reference clock frequency is selected via cfg_srds_sgmii_refclk during POR frequency band from 150 kHz to 15 MHz, at BER of 10E-12. 3. Total peak-to-peak deterministic jitter “Dj” should be less than or equal to 50 ps. MPC8536E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 3 Freescale Semiconductor Ethernet: Enhanced Three-Speed Ethernet (eTSEC), MII Management Min — ...

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... XMITEQAB (for SerDes 2 lanes OD A & XMITEQEF (for SerDes 2 lanes E & E) bit field of MPC8536E’s SerDes 2 Control Register: • The MSbit (bit 0) of the above bit field is set to zero (selecting the full V • ...

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... Figure 30. SGMII Transmitter DC Measurement Circuit Table 40. SGMII DC Receiver Electrical Characteristics Parameter Supply Voltage DC Input voltage range Input differential voltage LSTS = 0 LSTS = 1 MPC8536E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 3 Freescale Semiconductor Ethernet: Enhanced Three-Speed Ethernet (eTSEC), MII Management SD2_TXn 50 Ω SD_RXm Ω ...

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... The concept of this parameter is equivalent to the Electrical Idle Detect Threshold parameter in PCI Express. See PCI Express Differential Receiver (RX) Input Specifications section for further explanation. 4. The LSTS shown in the table refers to the LSTSA or LSTSE bit field of MPC8536’s SerDes 2 Control Register also referred to as peak to peak AC common mode voltage. ...

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... V /2 RX_DIFFp-p-max V /2 RX_DIFFp-p-min - V /2 RX_DIFFp-p-min − RX_DIFFp-p-max Figure 31. SGMII Receiver Input Compliance Mask MPC8536E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 3 Freescale Semiconductor Ethernet: Enhanced Three-Speed Ethernet (eTSEC), MII Management = 1.0V ± 5%. DD Symbol Min JD 0.37 JDR 0.55 JSIN 0 ...

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... Figure 33. eTSEC IEEE 1588 Output AC timing 1 The output delay is count starting rising edge if t Figure 34 provides the data and command input timing diagram. TSEC_1588_CLK TSEC_1588_TRIG_IN Figure 34. eTSEC IEEE 1588 Input AC timing MPC8536E PowerQUICC III Integrated Processor Hardware Specifications, Rev T1588CLKOUT t T1588CLKOUTH t T1588OV is non-inverting ...

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... See the MPC8536E PowerQUICC III Integrated Communications Processor Reference Manual for a description of TMR_CTRL registers need least two times of clock period of clock selected by TMR_CTRL[CKSEL]. See the MPC8536E PowerQUICC III Integrated Processor Reference Manual for a description of TMR_CTRL registers. 2.10 ...

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... Table 45. MII Management AC Timing Specifications At recommended operating conditions with OVDD is 3.3 V ± 5%. Parameter/Condition EC_MDC frequency EC_MDC period EC_MDC clock pulse width high EC_MDC to EC_MDIO delay EC_MDIO to EC_MDC setup time MPC8536E PowerQUICC III Integrated Processor Hardware Specifications, Rev Table 44. Symbol Min OV 3.13 ...

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... EC_MDC output clock frequency for a specific eTSEC port can be programmed by configuring the MgmtClk bit field of MPC8536E’s MIIMCFG register, based on the platform (CCB) clock running for the device. The formula is: Platform Frequency (CCB)/(2*Frequency Divider determined by MIICFG[MgmtClk] encoding selection). For example, if ...

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... OV IN 2.11.2 USB AC Electrical Specifications Table 47 describes the general timing parameters of the USB interface of the MPC8536E. Parameter usb clock cycle time Input setup to usb clock - all inputs input hold to usb clock - all inputs usb clock to output valid - all outputs ...

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... Figure 36 and Figure 37 provide the AC test load and signals for the USB, respectively. Output USB0_CLK/USB1_CLK/DR_CLK Input Signals Output Signals: MPC8536E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 3 Freescale Semiconductor = 50 Ω Ω Figure 36. USB AC Test Load t USIVKH t t USKHOX USKHOV Figure 37. USB Signals ...

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... Local Bus Controller (eLBC) 2.12 enhanced Local Bus Controller (eLBC) This section describes the DC and AC electrical specifications for the local bus interface of the MPC8536E. 2.12.1 Local Bus DC Electrical Characteristics Table 48 provides the DC electrical characteristics for the local bus interface operating at BV Table 48 ...

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... Local bus clock to data valid for LAD/LDP Local bus clock to address valid for LAD Local bus clock to LALE assertion Output hold from local bus clock (except LAD/LDP and LALE) MPC8536E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 3 Freescale Semiconductor Symbol Condition BV — ...

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... Local bus clock to address valid for LAD Local bus clock to LALE assertion Output hold from local bus clock (except LAD/LDP and LALE) MPC8536E PowerQUICC III Integrated Processor Hardware Specifications, Rev (First two letters of functional block)(signal)(state) (reference)(state) for outputs. For example, t ...

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... Local bus clock to data valid for LAD/LDP Local bus clock to address valid for LAD Local bus clock to LALE assertion Output hold from local bus clock (except LAD/LDP and LALE) MPC8536E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 3 Freescale Semiconductor Configuration Symbol — ...

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... Maximum possible clock skew between a clock LCLK[m] and a relative clock LCLK[n]. Skew measured between complementary signals at BV /2. DD Figure 38 provides the AC test load for the local bus. Output MPC8536E PowerQUICC III Integrated Processor Hardware Specifications, Rev Configuration Symbol — — — (First two letters of functional block)(signal)(state) (reference)(state) for outputs ...

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... LCLK[n] to that used in PLL Enable Mode. In this mode, output signals are launched at the falling edge of the LCLK[n] and inputs signals are captured at the rising edge of LCLK[n] with the exception of LGTA/LUPWAIT (which is captured at the falling edge of the LCLK[n]). MPC8536E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 3 Freescale Semiconductor t LBIVKH1 ...

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... Input hold from local bus clock (except LUPWAIT) LUPWAIT input hold from local bus clock LALE output transition to LAD/LDP output transition (LATCH hold time) Local bus clock to output valid (except LAD/LDP and LALE) MPC8536E PowerQUICC III Integrated Processor Hardware Specifications, Rev LBIVKL2 t ...

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... These timing parameters for PLL bypass mode are defined in the opposite direction of the PLL enabled output hold timing parameters. MPC8536E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 3 Freescale Semiconductor enhanced Local Bus Controller (eLBC) ...

Page 74

... GPCM Mode Input Signal: LGTA UPM Mode Input Signal: LUPWAIT Input Signals: LAD[0:31]/LDP[0:3] UPM Mode Output Signals: LCS[0:7]/LBS[0:3]/LGPL[0:5] Figure 41. Local Bus Signals, GPCM/UPM Signals for LCRR[CLKDIV] = 4(PLL Enabled) MPC8536E PowerQUICC III Integrated Processor Hardware Specifications, Rev LBKHOZ1 t LBKHOV1 t LBIVKH2 t ...

Page 75

... LCS[0:7]/LBS[0:3]/LGPL[0:5] Figure 42. Local Bus Signals, GPCM/UPM Signals for LCRR[CLKDIV 16(PLL Enabled) 2.13 Enhanced Secure Digital Host Controller (eSDHC) This section describes the DC and AC electrical specifications for the eSDHC interface of the MPC8536E. 2.13.1 eSDHC DC Electrical Characteristics Table 55 provides the DC electrical characteristics for the eSDHC interface of the MPC8536E. ...

Page 76

... Hz means to stop the clock. The given minimum frequency range is for cases were a continuous clock is required satisfy hold timing, the delay difference between clock input and cmd/data input must not exceed 2ns. ≤10 pF, (1 card), and CARD L MPC8536E PowerQUICC III Integrated Processor Hardware Specifications, Rev Table 3) Condition I = 100uA @OVDDmin ...

Page 77

... In IRQ edge trigger mode, when an external interrupt signal is asserted (according to the programmed polarity), it must remain the assertion for at least 3 system clocks (SYSCLK periods). 2.15 JTAG This section describes the DC and AC electrical specifications for the IEEE 1149.1 (JTAG) interface of the MPC8536E. 2.15.1 JTAG DC Electrical Characteristics Table 57 provides the DC electrical characteristics for the JTAG interface ...

Page 78

... Notes: 1. Note that the symbol V IN 2.15.2 JTAG AC Electrical Specifications This section describes the AC electrical specifications for the IEEE 1149.1 (JTAG) interface of the MPC8536E. Table 58 provides the JTAG AC timing specifications as defined in Table 58. JTAG AC Timing Specifications (Independent of SYSCLK) At recommended operating conditions (see ...

Page 79

... Serial ATA (SATA) This section describes the DC and AC electrical specifications for the serial ATA (SATA) of the MPC8536E. Note that the external cabled applications or long backplane applications (Gen1x & Gen2x) are not supported. MPC8536E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 3 Freescale Semiconductor = 50 Ω ...

Page 80

... Only 100/125/150 MHz have been tested, other in between values will not work correctly with the rest of the system frequency band from 150 kHz to 15 MHz, at BER of 10E-12. 3. Total peak-to-peak deterministic jitter “Dj” should be less than or equal to 50 ps. Ref_CLK Figure 49. Reference Clock Timing Waveform MPC8536E PowerQUICC III Integrated Processor Hardware Specifications, Rev Table 59. Symbol ...

Page 81

... MHz - 300 MHz 300 MHz - 600 MHz 600 MHz - 1.2 GHz RL SATA_TXDD11 1.2 GHz - 2.4 GHz 2.4 GHz - 3.0 GHz 3.0 GHz - 5.0 GHz MPC8536E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 3 Freescale Semiconductor Symbol Min Typical — 1.5 3.0 T 666 ...

Page 82

... Notes: 1. Only applies when operating in 3.0Gb data rate mode. 2. The max value stated for 3.0 GHz - 5.0 GHz range only applies to Gen2i mode and not to Gen2m mode. 3. Only applies to Gen1i mode. MPC8536E PowerQUICC III Integrated Processor Hardware Specifications, Rev Symbol Min Typical — ...

Page 83

... SATA_RXSKEW 3.0G RX Differential pair impedance 1.5G Z SATA_RXDIFFIM RX Single-Ended impedance Z SATA_RXSEIM 1.5G DC Coupled Common Mode V dc_cm Voltage MPC8536E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 3 Freescale Semiconductor 80% 80% t SATA_20-80TXfall TX+ TX- EARLY (TX+ is early) Min Typical Max 240 400 600 240 — 750 100 — ...

Page 84

... The max value stated for 3.0 GHz - 5.0 GHz range only applies to Gen2i mode and not to Gen2m mode. 4. The max value stated for 2.4 GHz - 3.0 GHz range only applies to Gen2i mode for Gen2m the value Only applies to Gen1i mode. MPC8536E PowerQUICC III Integrated Processor Hardware Specifications, Rev Min ...

Page 85

... Out-of-Band (OOB) Electrical Characteristics Table 62 provides the Out-of-Band (OOB) electrical characteristics for the SATA interface of the MPC8536E. Table 62. Out-of-Band (OOB) Electrical Characteristics Parameter OOB Signal Detection Threshold 1.5G 3.0G UI During OOB Signaling COMINIT/ COMRESET and COMWAKE Transmit Burst Length COMINIT/ COMRESET Transmit Gap Length T ...

Page 86

... Capacitance for each I/O pin Notes: 1. Output voltage (open drain or open collector) condition = 3 mA sink current. 2. See the MPC8536E PowerQUICC III Integrated Processor Reference Manual for information on the digital filter used. 3. I/O pins will obstruct the SDA and SCL lines 2.17.2 ...

Page 87

... For rise and fall times, the latter convention is used with the appropriate letter: R (rise (fall transmitter, the MPC8536E provides a delay time of at least 300 ns for the SDA signal (referred to the Vihmin of the SCL signal) to bridge the undefined region of the falling edge of SCL to avoid unintended generation of Start or Stop condition. ...

Page 88

... GPIO 2.18 GPIO This section describes the DC and AC electrical specifications for the GPIO interface of the MPC8536E. 2.18.1 GPIO DC Electrical Characteristics Table 65 provides the DC electrical characteristics for the GPIO interface. Table 65. GPIO DC Electrical Characteristics Parameter High-level input voltage Low-level input voltage Input current ...

Page 89

... PCI This section describes the DC and AC electrical specifications for the PCI bus of the MPC8536E. 2.19.1 PCI DC Electrical Characteristics Table 67 provides the DC electrical characteristics for the PCI interface. Table 67. PCI DC Electrical Characteristics Parameter High-level input voltage Low-level input voltage Input current ...

Page 90

... The reset assertion timing requirement for HRESET is 100 μs. Figure 54 provides the AC test load for PCI. Output Figure 55 shows the PCI input AC timing conditions. CLK Input Figure 55. PCI Input AC Timing Measurement Conditions MPC8536E PowerQUICC III Integrated Processor Hardware Specifications, Rev Symbol t PCRHFV t PCICLK t ...

Page 91

... High-Speed Serial Interfaces The MPC8536E features two Serializer/Deserializer (SerDes) interfaces to be used for high-speed serial interconnect applications. The SerDes1 interface is dedicated for PCI Express data transfers. The SerDes2 can be used for SGMII or SATA. This section describes the common portion of SerDes DC electrical specifications, which is the DC requirement for SerDes Reference Clocks. The SerDes data lane’ ...

Page 92

... SerDes Reference Clock Receiver Reference Circuit Structure — The SDn_REF_CLK and SDn_REF_CLK are internally AC-coupled differential inputs as shown in Each differential clock input (SDn_REF_CLK or SDn_REF_CLK) has a 50-Ω termination to SGND (xcorevss) followed by on-chip AC-coupling. MPC8536E PowerQUICC III Integrated Processor Hardware Specifications, Rev ...

Page 93

... DC exceeds the maximum input current limitations, then it must be AC-coupled off-chip. • The input amplitude requirement — This requirement is described in detail in the following sections. SDn_REF_CLK SDn_REF_CLK Figure 58. Receiver of SerDes Reference Clocks MPC8536E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 3 Freescale Semiconductor High-Speed Serial Interfaces 50 Ω Input Amp 50 Ω ...

Page 94

... High-Speed Serial Interfaces 2.20.2.2 DC Level Requirement for SerDes Reference Clocks The DC level requirement for the MPC8536E SerDes reference clock inputs is different depending on the signaling mode used to connect the clock driver chip and SerDes reference clock inputs as described below. • Differential Mode — ...

Page 95

... The system designer is recommended to contact the selected clock driver chip vendor for the optimal reference circuits with the MPC8536E SerDes reference clock receiver requirement provided in this document. MPC8536E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 3 ...

Page 96

... SerDes reference clock connection reference circuits for LVDS type clock driver. Since LVDS clock driver’s common mode voltage is higher than the MPC8536E SerDes reference clock input’s allowed range (100 to 400mV), AC-coupled connection scheme must be used. It assumes the LVDS output driver features 50-Ω termination resistor. It also assumes that the LVDS transmitter establishes its own common mode level without relying on the receiver or other external component ...

Page 97

... R2 is used together with the SerDes reference clock receiver’s 50-Ω termination resistor to attenuate the LVPECL output’s differential peak level such that it meets the MPC8536E SerDes reference clock’s differential input amplitude requirement (between 200mV and 800mV differential peak). For example, if the LVPECL output’s differential peak is 900mV and the desired SerDes reference clock input amplitude is selected as 600mV, the attenuation factor is 0.67, which requires R2 = 25Ω ...

Page 98

... See Rise Edge Rate V = +200 –200 mV IL – _REF_CLK SD n _REF_CLK Figure 66. Differential Measurement Points for Rise and Fall Time MPC8536E PowerQUICC III Integrated Processor Hardware Specifications, Rev 1.0V ± 5%. DD_SRDS1 DD_SRDS2 Symbol Rise Edge Rate Fall Edge Rate ...

Page 99

... Section 2.16, “Serial ATA (SATA)” Please note that external AC Coupling capacitor is required for the above three serial transmission protocols with the capacitor value defined in specification of each protocol section. MPC8536E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 3 Freescale Semiconductor Clocks” ...

Page 100

... PCI Express 2.21 PCI Express This section describes the DC and AC electrical specifications for the PCI Express bus of the MPC8536E. 2.21.1 DC Requirements for PCI Express SD1_REF_CLK and SD1_REF_CLK For more information, see Section 2.20.2, “SerDes Reference Clocks.” 2.21.2 AC Requirements for PCI Express SerDes Clocks Table 70 lists AC requirements ...

Page 101

Table 71. Differential Transmitter (TX) Output Specifications (continued) Symbol Parameter V De- Emphasized TX-DE-RATIO Differential Output Voltage (Ratio) T Minimum TX Eye TX-EYE Width T Maximum time TX-EYE-MEDIAN-to- between the jitter MAX-JITTER median and maximum deviation from the median. T ...

Page 102

... Measured between 20-80% at transmitter package pins into a test load as shown in 6. See Section 4.3.1.8 of the PCI Express Base Specifications Rev 1.0a 7. See Section 4.2.6.3 of the PCI Express Base Specifications Rev 1.0a 8. SerDes transmitter does not have C MPC8536E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 3 102 Min Nom ...

Page 103

Transmitter Compliance Eye Diagrams The TX eye diagram in Figure 69 any real PCI Express interconnect + RX component. There are two eye diagrams that must be met for the transmitter. Both eye diagrams must be aligned in time ...

Page 104

... Powered Down RX-HIGH-IMP-DC DC Input Impedance V Electrical Idle RX-IDLE-DET-DIFFp-p Detect Threshold T Unexpected RX-IDLE-DET-DIFF- Electrical Idle ENTERTIME Enter Detect Threshold Integration Time MPC8536E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 3 104 Min Nom Max Units 0.4 — — UI — — 0.3 UI — — ...

Page 105

... The eye diagram must be valid for any 250 consecutive UIs. A recovered calculated over 3500 consecutive unit intervals of sample data. The eye diagram is created using all edges of the 250 consecutive UI in the center of the 3500 UI used for calculating the TX UI. MPC8536E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 3 Freescale Semiconductor Min ...

Page 106

... D+ Package D+ Package D– Package Figure 71. Compliance Test/Measurement Load 2.23 Clocking This section describes the PLL configuration of the MPC8536E. Note that the platform clock is identical to the core complex bus (CCB) clock. MPC8536E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 3 106 NOTE Figure 71 ...

Page 107

... Section 2.23.2, “CCB/SYSCLK PLL Section 2.23.4, “DDR/DDRCLK PLL Ratio,” 2. The Memory bus clock refers to the MPC8536E memory controllers’ MCK[0:5] and MCK[0:5] output clocks, running at half of the DDR data rate synchronous mode, the memory bus clock speed is half the platform clock frequency. In other words, the DDR data rate is the same as the platform (CCB) frequency ...

Page 108

... PLL rate in asynchronous mode. In asynchronous mode, the DDR PLL rate to DDRCLK ratios listed in since the DDR PLL rate in asynchronous mode means the DDR data rate resulting from DDR PLL output. MPC8536E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 3 108 Table 75: Table 75 ...

Page 109

... TSEC1_1588_CLK_OUT 2.23.5 PCI Clocks The integrated PCI controller in MPC8536E supports PCI input clock frequency in the range of 33–66 MHz. The PCI input clock can be applied from SYSCLK in synchronous mode or PCI1_CLK in asynchronous mode. For specifications on the PCI1_CLK, refer to the PCI 2.2 Specification. ...

Page 110

... Minimum Platform Frequency Requirements for High-speed Interfaces Section 4.4.3.8 “SerDes1 I/O Port Selection” and Section 4.4.3.9 “SerDes2 I/O Port Selection” of the MPC8536E PowerQUICC III Integrated Host Processor Family Reference Manual, describes various high-speed interface configuration options. Note that the CCB clock frequency must be considered for proper operation of such interfaces as described below. ...

Page 111

... SPEC-883 Method 1012.1) with the calculated case temperature. Actual thermal resistance is less than 0.1 •C/W Simulations with heat sinks were done with the package mounted on the 2s2p thermal test board. The thermal interface material was a typical thermal grease such as Dow Corning 340 or Wakefield 120 grease.For system thermal modeling, the MPC8536E thermal model without a lid is shown in conductivity of 19.8 W/m• ...

Page 112

... Ky Kz Figure 72. System Level Thermal Model for MPC8536E (Not to Scale) The Flotherm library files of the parts have a dense grid to accurately capture the laminar boundary layer for flow over the part in standard JEDEC environments, as well as the heat spreading in the board under the package real system, however, the part will require a heat sink to be mounted on it ...

Page 113

... Several heat sinks offered by Aavid Thermalloy, Advanced Thermal Solutions, Alpha Novatech, IERC, Chip Coolers, Millennium Electronics, and Wakefield Engineering offer different heat sink-to-ambient thermal resistances, that will allow the MPC8536E to function in various environments. 2.24.3.1 Internal Package Conduction Resistance For the packaging technology, shown in • ...

Page 114

... This performance characteristic chart is generally provided by the thermal interface vendors. 3 Hardware Design Considerations This section provides electrical and thermal design recommendations for successful application of the MPC8536E. 3.1 System Clocking This device includes seven PLLs: • ...

Page 115

... This noise must be prevented from reaching other components in the MPC8536E system, and the device itself requires a clean, tightly regulated source of power. Therefore recommended that the system designer place at least one decoupling capacitor at each V and LV pin of the device ...

Page 116

... See the PCI 2.2 specification for all pull-ups required for PCI. 3.8 Output Buffer DC Impedance The MPC8536E drivers are characterized over process, voltage, and temperature. For all buses, the driver is a push-pull single-ended driver type (open drain for I MPC8536E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 3 ...

Page 117

... Configuration Pin Muxing The MPC8536E provides the user with power-on configuration options which can be set through the use of external pull-up or pull-down resistors of 4.7 kΩ on certain output pins (see customer visible configuration pins). These pins are generally used as output only pins in normal operation. ...

Page 118

... TRST in case a JTAG interface may need to be wired onto the system in future debug situations. • No pull-up/pull-down is required for TDI, TMS, or TDO. MPC8536E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 3 118 allows the COP port to independently assert HRESET or TRST, while ensuring that the Figure 79, for connection to the target system, and is based on the 0.025" ...

Page 119

... This switch is included as a precaution for BSDL testing. The switch should be closed to position A during BSDL testing to avoid accidentally asserting the TRST line. If BSDL testing is not being performed, this switch should be closed to position B. 6. Asserting SRESET causes a machine check interrupt to the e500 core. MPC8536E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 3 Freescale Semiconductor COP_HRESET COP_SRESET ...

Page 120

... If only part of the high speed SerDes interface pins are used, the remaining high-speed serial I/O pins should be terminated as described in this section. The following pins must be left unconnected (float) if not used: • SD1_TX[7:0] • SD1_TX[7:0] • Reserved pins: T22, T23 MPC8536E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 3 120 2 COP_TDO COP_TDI 3 ...

Page 121

... SD2_RX[1:0] • SD2_RX[1:0] 4 Ordering Information Ordering information for the parts fully covered by this specification document is provided in Addressed by This Document.” MPC8536E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 3 Freescale Semiconductor Guidelines for High-Speed Interface Termination Section 4.1, “Part Numbers Fully 121 ...

Page 122

... Processor core frequencies supported by parts addressed by this specification only. Not all parts described in this specification support all core frequencies. Additionally, parts addressed by part number specifications may support other maximum core frequencies. 3. See Table 84 for the corresponding maximum platform frequency. MPC8536E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 3 122 Table 82. Device Nomenclature ...

Page 123

... CCCCC is the country of assembly. This space is left blank if parts are assembled in the United States. Figure 80. Part Marking for FC-PBGA Device 4.3 Part Numbering Table 83 and Table 84 list all part numbers that are offered for MPC8536E. Table 83. MPC8536 Part Numbers Commercial Tier Core/Platform/DDR (MHz) Standard Temp Without Security 600/400/400 800/400/400 1000/400/400 ...

Page 124

... Package outline Interconnects Pitch Minimum module height Maximum module height Solder Balls Ball diameter (typical) MPC8536E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 3 124 Standard Temp Extended Temp With Security Without Security FC-PBGA MPC8536E 29 mm × ...

Page 125

... Mechanical Dimensions of the MPC8536E FC-PBGA The mechanical dimensions and bottom surface nomenclature of the MPC8536E, 783 FC-PBGA package are shown in Figure 81. Figure 81. Mechanical Dimensions and Bottom Surface Nomenclature of the MPC8536E FC-PBGA 1. All dimensions are in millimeters. 2. Dimensions and tolerances per ASME Y14.5M-1994. ...

Page 126

... Date 3 11/2010 • In Table 1, “MPC8536E Pinout Listing,” added the following note: “For systems that boot from Local Bus(GPCM)-controlled NOR flash or (FCM) controlled NAND flash, a pullup on LGPL4 is required...” In addition, updated footnote 26 and added footnote 29 to PCI1_AD. • Updated • Updated • ...

Page 127

... For Literature Requests Only: Freescale Semiconductor Literature Distribution Center 1-800-441-2447 or +303-675-2140 Fax: +303-675-2150 LDCForFreescaleSemiconductor@hibbertgroup.com Document Number: MPC8536EEC Rev. 3 11/2010 Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document ...